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Sta Static Timing Analysis Engineer Jobs in Chicago, IL

Eliyan

PD - IP Lead - Sr Staff, Physical Design

Mundelein, IL · On-site

$138.80K - $142.90K/yr

As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... PNR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical ...

DRW

Senior FPGA Engineer (Algo)

Chicago, IL · On-site

$150K - $250K/yr

Architect and implement new FPGA applications (synthesis, place & route, static timing analysis ... Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ...

Eliyan

PD - Principal, Physical Design

Mundelein, IL · On-site

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... PnR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical ...

Akuna Capital

Senior FPGA Engineer

Chicago, IL

$107.10K - $144.20K/yr

What you'll do as a Senior FPGA Engineer at Akuna: We are looking for Senior FPGA Engineers to ... Solid grasp of static timing analysis, synthesis, and place-and-route tools * Familiarity with ...

Akuna Capital

Senior FPGA Engineer

Chicago, IL

$145K/yr

What you'll do as a Senior FPGA Engineer at Akuna: We are looking for Senior FPGA Engineers to ... Solid grasp of static timing analysis, synthesis, and place-and-route tools * Familiarity with ...

Akuna Capital

Senior FPGA Engineer

Chicago, IL · On-site

$145K/yr

What you'll do as a Senior FPGA Engineer at Akuna: We are looking for Senior FPGA Engineers to ... Solid grasp of static timing analysis, synthesis, and place-and-route tools * Familiarity with ...

Shure

Engineer Staff Managing, FPGA

Niles, IL · On-site

$130.70K - $167.90K/yr

... static timing analysis. • Solid knowledge of digital signal processing techniques, embedded ... We engineer microphones, headphones, wireless audio systems, conferencing systems, and more. And ...

Shure

Engineer Staff Managing, FPGA

Niles, IL

$130.70K - $167.90K/yr

... static timing analysis. • Solid knowledge of digital signal processing techniques, embedded ... We engineer microphones, headphones, wireless audio systems, conferencing systems, and more. And ...

Shure

Engineer Staff Managing, FPGA

Niles, IL

... route, and static timing analysis. Solid knowledge of digital signal processing techniques ... We engineer microphones, headphones, wireless audio systems, conferencing systems, and more. And ...

Shure

Engineer Staff Managing, FPGA

Niles, IL

... route, and static timing analysis. Solid knowledge of digital signal processing techniques ... We engineer microphones, headphones, wireless audio systems, conferencing systems, and more. And ...

CB&I

Analysis Engineer (Structural)

Plainfield, IL · On-site

Perform finite element analysis of plate steel and concrete structures for static, thermal and ... Professional Engineering (P.E.) license in at least one state or EIT with the ability to obtain a P.

CB&I

Senior Analysis Engineer (Structural)

Plainfield, IL · On-site

$98K - $133K/yr

Expert in performing finite element analysis of plate steel and concrete structures for static ... Professional Engineering (P.E.) license in at least one state or with the ability to obtain a P.E ...

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Sta Static Timing Analysis Engineer information

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How much do sta static timing analysis engineer jobs pay per hour?

As of May 28, 2026, the average hourly pay for sta static timing analysis engineer in Chicago, IL is $55.25, according to ZipRecruiter salary data. Most workers in this role earn between $44.57 and $64.13 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Static Timing Analysis (STA) Engineer, and why are they important?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are some common challenges faced by STA Static Timing Analysis Engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are STA (Static Timing Analysis) Engineers?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.
What are popular job titles related to Sta Static Timing Analysis Engineer jobs in Chicago, IL? For Sta Static Timing Analysis Engineer jobs in Chicago, IL, the most frequently searched job titles are:
What job categories do people searching Sta Static Timing Analysis Engineer jobs in Chicago, IL look for? The top searched job categories for Sta Static Timing Analysis Engineer jobs in Chicago, IL are:
Sta Static Timing Analysis Engineer jobs near you

PD - IP Lead - Sr Staff, Physical Design

Eliyan

Mundelein, IL • On-site

$138.80K - $142.90K/yr

Full-time

Posted 17 days ago

Job description

Join the leading chiplet startup! As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII.  You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PNR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV – DRC, LVS, Antenna). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits.
Responsibilities:
  • Define and execute IP block and partition physical design strategy across projects, aligning schedules, resources, and milestones to company tapeout goals.
  • Lead mixed signal placement and routing, enforcing analog keepouts, shielding, and DRC aware methodologies while integrating digital logic cleanly.
  • Own system and block integration for floorplanning, power, placement, CTS, and constraints, ensuring consistent interfaces across hierarchy and reuse
  • Drive end to end IP physical implementation from RTL handoff through GDSII, managing iterations, ECOs, and closure plans across corners
  • Develop and maintain block specific flow customizations for synthesis, PNR, EM IR, STA, and physical verification to improve QoR and predictability
  • Deliver robust constraints methodology, pushing timing intent from system to block and back, maintaining mode and corner correctness for signoff
  • Run and close subsystem signoff including STA, EM IR, SI, DRC, LVS, antenna, and metal fill, meeting reliability and manufacturability requirements
  • Optimize clock architecture and CTS for skew, latency, and power, including skew group definitions and balancing across library corners
  • Collaborate with front end, DFT, packaging, and manufacturing to resolve integration risks, test mode impacts, and physical interface requirements
  • Provide clear status, risk, and mitigation reporting to leadership, using metrics driven dashboards for PPA, convergence, and schedule predictability
Minimum Qualifications:
  • Expertise in physical design, timing closure, and signoff for small to large ASIC IP blocks, including mixed signal integration and subsystem closure ownership
  • Strong hands-on experience with floorplanning, power planning, placement, CTS, routing, EM IR, STA, and PV signoff across MMMC scenarios
  • Proven ability to improve flows through automation and scripting, with disciplined debug skills and data driven QoR and runtime optimization mindset
  • Excellent cross functional leadership and communication skills to drive alignment, technical reviews, and closure decisions under aggressive timelines

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.