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Soc Low Power Engineer Jobs (NOW HIRING)

... time, low power and high performance execution of Deep Learning workloads. Our success is the ... SoC low level software development, distributed computing or hardware acceleration Strong ...

Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge ... Silicon Engineering Power team. Your contributions will enable the creation of chips with ...

Please look for design engineers with power analysis experience Verification engineers with power aware verification or low power design verification experience. ASIC/SOC power engineers with ...

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How much do soc low power engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for soc low power engineer in the United States is $123,502.00, according to ZipRecruiter salary data. Most workers in this role earn between $112,000.00 and $132,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Soc Low Power Engineer job openings in the United States as of September 2026, with employment types broken down into 86% Full Time, and 14% Contract. Highlights an 100% In-person job distribution, with an average salary of $123,502 per year, or $59.4 per hour.

RTL Power Engineer (Only W2)

Mountain View, CA โ€ข On-site

Other

Posted 13 days ago


Job description

RTL Power Engineer

 

The CPU Power Team wants a talented
individual contributor engineer to own and drive several activities related
to CPU architecture and system level energy modeling, competitive performance
and power analysis, power optimization, simulation and rollups.

Develop novel power analysis techniques, optimization engines and other
tooling solutions to improve the battery life analysis and maximize the
energy efficiency of our CPU

The qualified engineer will collaborate with the SoC and CPU Power Team on
power analysis and projections and requirements for our CPU. This charter
includes profiling the power of typical workloads such as YouTube, Facebook,
etc

Perform workload analysis for battery life and tests definition for power
analysis and optimization

Perform data mining analysis at the RTL and gate-level to define relevant
micro-architectural transactions for high-level power estimation.

MINIMUM QUALIFICATIONS

BS in Electrical Engineering, Computer Science, or equivalent practical
experience 3 years of experience in industry (e.g. Hardware, etc.) or
equivalent research Experience with low-power fundamentals (e.g., dynamic
and leakage, power estimation, and optimization), data analytics and
profiling

Experience in flow automation (Python, C, C++, Gemini)

Expertise in vendor tools such as PTPX, Ansys Power Artist, Synopsys Prime
Power RTL PREFERRED QUALIFICATIONS

3-5 years of experience in RTL design and low-power design techniques
Familiar with the concept of power management, retention, DVFS

Experience with data science

Familiar with CPU benchmarking, performance analysis and competitive study
Demonstrated knowledge of CPU microarchitecture and system level