... the SoC and CPU Power Team on power analysis and projections and requirements for our CPU. This ... Hardware, etc.) or equivalent research Experience with low-power fundamentals (e.g., dynamic and ...
... the SoC and CPU Power Team on power analysis and projections and requirements for our CPU. This ... Hardware, etc.) or equivalent research Experience with low-power fundamentals (e.g., dynamic and ...
You will collaborate with experienced designers, RTL engineers, system and software team, to ... power SoC design, including arch features, RTL changes for low power design, topologies with ...
You will collaborate with experienced designers, RTL engineers, system and software team, to ... power SoC design, including arch features, RTL changes for low power design, topologies with ...
You will collaborate with experienced designers, RTL engineers, system and software team, to ... power SoC design, including arch features, RTL changes for low power design, topologies with ...
You will collaborate with experienced designers, RTL engineers, system and software team, to ... power SoC design, including arch features, RTL changes for low power design, topologies with ...
Engineering Group, Engineering Group > ASICS Engineering General Summary: Job Overview: * Design ... Support SoC team to integrate low power / power management IP solution into wireless SoC chips and ...
Engineering Group, Engineering Group > ASICS Engineering General Summary: Job Overview: * Design ... Support SoC team to integrate low power / power management IP solution into wireless SoC chips and ...
Low Power Design/Methodology Engineer
San Diego, CA ยท On-site
$115K - $173K/yr
Support SoC team to integrate low power / power management IP solution into wireless SoC chips and ... Understanding of electrical engineering concepts, circuit analysis and logic design skills.
Low Power Design/Methodology Engineer
San Diego, CA ยท On-site
$115K - $173K/yr
Support SoC team to integrate low power / power management IP solution into wireless SoC chips and ... Understanding of electrical engineering concepts, circuit analysis and logic design skills.
Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology ... Work with design verification in validating low power design featurs at SoC and IP level.
Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology ... Work with design verification in validating low power design featurs at SoC and IP level.
Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology ... Work with design verification in validating low power design featurs at SoC and IP level.
Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology ... Work with design verification in validating low power design featurs at SoC and IP level.
... SoC) development for a variety of high performance, high quality ... low power world class products. Qualcomm Engineers collaborate with cross-functional groups to ...
... SoC) development for a variety of high performance, high quality ... low power world class products. Qualcomm Engineers collaborate with cross-functional groups to ...
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and ... SOC power modeling, low power design and power optimization experience is a plus Strong ...
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and ... SOC power modeling, low power design and power optimization experience is a plus Strong ...
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and ... SOC power modeling, low power design and power optimization experience is a plus Strong ...
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and ... SOC power modeling, low power design and power optimization experience is a plus Strong ...
ANE Pre-Silicon Driver Engineer
Sunnyvale, CA ยท On-site
... time, low power and high performance execution of Deep Learning workloads. Our success is the ... SoC low level software development, distributed computing or hardware acceleration Strong ...
ANE Pre-Silicon Driver Engineer
Sunnyvale, CA ยท On-site
... time, low power and high performance execution of Deep Learning workloads. Our success is the ... SoC low level software development, distributed computing or hardware acceleration Strong ...
Design Engineer V
Sunnyvale, CA ยท Hybrid
... in low power design, tools and methodologies including power intent UPF specifications Silicon ... power profiling experience at IP/SoC level
Design Engineer V
Sunnyvale, CA ยท Hybrid
... in low power design, tools and methodologies including power intent UPF specifications Silicon ... power profiling experience at IP/SoC level
Design Engineer V
Sunnyvale, CA ยท On-site
... in low power design, tools and methodologies including power intent UPF specifications Silicon ... power profiling experience at IP/SoC level
Design Engineer V
Sunnyvale, CA ยท On-site
... in low power design, tools and methodologies including power intent UPF specifications Silicon ... power profiling experience at IP/SoC level
Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge ... Silicon Engineering Power team. Your contributions will enable the creation of chips with ...
Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge ... Silicon Engineering Power team. Your contributions will enable the creation of chips with ...
Power Engineer (RTL Design)
Sunnyvale, CA ยท On-site
Please look for design engineers with power analysis experience Verification engineers with power aware verification or low power design verification experience. ASIC/SOC power engineers with ...
Quick apply
Power Engineer (RTL Design)
Sunnyvale, CA ยท On-site
Please look for design engineers with power analysis experience Verification engineers with power aware verification or low power design verification experience. ASIC/SOC power engineers with ...
SoC Power Architecture Engineer - Processor Subsystem
Saratoga, CA ยท On-site
$150K - $220K/yr
We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change ... We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement ...
SoC Power Architecture Engineer - Processor Subsystem
Saratoga, CA ยท On-site
$150K - $220K/yr
We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change ... We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement ...
SoC Power Architecture Engineer - Processor Subsystem
Saratoga, CA ยท On-site
$150K - $220K/yr
We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change ... We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement ...
Quick apply
SoC Power Architecture Engineer - Processor Subsystem
Saratoga, CA ยท On-site
$150K - $220K/yr
We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change ... We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement ...
SoC Power Architecture Engineer - Processor Subsystem
Saratoga, CA ยท On-site
$150K - $220K/yr
We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change ... We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement ...
SoC Power Architecture Engineer - Processor Subsystem
Saratoga, CA ยท On-site
$150K - $220K/yr
We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change ... We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement ...
SoC Power Analysis and Optimization Engineer
Austin, TX ยท On-site
$175K - $308K/yr
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and ... SOC power modeling, low power design and power optimization experience is a plus Strong ...
SoC Power Analysis and Optimization Engineer
Austin, TX ยท On-site
$175K - $308K/yr
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and ... SOC power modeling, low power design and power optimization experience is a plus Strong ...
SoC Power Analysis and Optimization Engineer
$142K - $263K/yr
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and ... SOC power modeling, low power design and power optimization experience is a plus Strong ...
SoC Power Analysis and Optimization Engineer
$142K - $263K/yr
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and ... SOC power modeling, low power design and power optimization experience is a plus Strong ...
Soc Low Power Engineer information
See salary details
$80.5K - $88.5K
9% of jobs
$88.5K - $96.6K
5% of jobs
$96.6K - $104.6K
6% of jobs
$111.9K is the 25th percentile. Wages below this are outliers.
$104.6K - $112.7K
5% of jobs
The median wage is $118.7K / yr.
$112.7K - $120.7K
33% of jobs
$120.7K - $128.8K
6% of jobs
$133K is the 75th percentile. Wages above this are outliers.
$128.8K - $136.8K
19% of jobs
$136.8K - $144.9K
4% of jobs
$144.9K - $152.9K
3% of jobs
$152.9K - $161K
3% of jobs
$161K - $169K
5% of jobs
$80.5K
$123.5K
$169K
How much do soc low power engineer jobs pay per year?
What are popular job titles related to Soc Low Power Engineer jobs?
For Soc Low Power Engineer jobs, the most frequently searched job titles are:

RTL Power Engineer (Only W2)
Mountain View, CA โข On-site
Other
Posted 13 days ago
Job description
RTL Power Engineer
The CPU Power Team wants a talented
individual contributor engineer to own and drive several activities related
to CPU architecture and system level energy modeling, competitive performance
and power analysis, power optimization, simulation and rollups.
Develop novel power analysis techniques, optimization engines and other
tooling solutions to improve the battery life analysis and maximize the
energy efficiency of our CPU
The qualified engineer will collaborate with the SoC and CPU Power Team on
power analysis and projections and requirements for our CPU. This charter
includes profiling the power of typical workloads such as YouTube, Facebook,
etc
Perform workload analysis for battery life and tests definition for power
analysis and optimization
Perform data mining analysis at the RTL and gate-level to define relevant
micro-architectural transactions for high-level power estimation.
MINIMUM QUALIFICATIONS
BS in Electrical Engineering, Computer Science, or equivalent practical
experience 3 years of experience in industry (e.g. Hardware, etc.) or
equivalent research Experience with low-power fundamentals (e.g., dynamic
and leakage, power estimation, and optimization), data analytics and
profiling
Experience in flow automation (Python, C, C++, Gemini)
Expertise in vendor tools such as PTPX, Ansys Power Artist, Synopsys Prime
Power RTL PREFERRED QUALIFICATIONS
3-5 years of experience in RTL design and low-power design techniques
Familiar with the concept of power management, retention, DVFS
Experience with data science
Familiar with CPU benchmarking, performance analysis and competitive study
Demonstrated knowledge of CPU microarchitecture and system level