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Soc Level 1 Jobs (NOW HIRING)

Apple

SoC Design Verification Engineer

Sunnyvale, CA

$161.80K - $197.50K/yr

This position gives you the opportunity to be a part of one of the most innovative and key projects ... As a member of this team you will integrate multiple sophisticated IP-level DV environments, craft ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$171.60K - $302.20K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... Expertise in SystemVerilog coding and UVM methodology Pay & Benefits At Apple, base pay is one part ...

Intel

SoC Design Engineer

Austin, TX · On-site

$122.44K - $232.19K/yr

You will be responsible for developing high-quality logic designs, coding register transfer level ... Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations:

Apple

SoC Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

This position gives you the opportunity to be a part of one of the most innovative and key projects ... As a member of this team you will integrate multiple sophisticated IP-level DV environments, craft ...

Apple

SoC Design Verification Engineer

Austin, TX

$126.80K - $220.90K/yr

This position gives you the opportunity to be a part of one of the most innovative and key projects ... As a member of this team you will integrate multiple sophisticated IP-level DV environments, craft ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$171.60K - $302.20K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... Expertise in SystemVerilog coding and UVM methodology Pay & Benefits At Apple, base pay is one part ...

Intel Corporation

SoC Design Engineer

Austin, TX · On-site

$122.44K - $232.19K/yr

You will be responsible for developing high-quality logic designs, coding register transfer level ... Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations:

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$171.60K - $302.20K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... Expertise in SystemVerilog coding and UVM methodology Pay & Benefits At Apple, base pay is one part ...

MatX

SOC Architect

Mountain View, CA · On-site +1

$175K - $450K/yr

Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing ... Learning & Development $1,500 yearly towards your professional development e.g. conferences ...

MatX

SOC Architect

Mountain View, CA · On-site

$175K - $450K/yr

Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing ... Learning & Development $1,500 yearly towards your professional development e.g. conferences ...

MatX

SOC Architect

Mountain View, CA · On-site +1

$175K - $450K/yr

Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing ... Learning & Development $1,500 yearly towards your professional development e.g. conferences ...

Qualcomm

SoC Performance Architect

Santa Clara, CA · On-site +1

$167K - $250.60K/yr

... in IP/SoC level performance validation between RTL and performance models, • Expertise in ... Even more importantly, please note that salary is only one component of total compensation at ...

Apple

Wireless SOC Verification Engineer

San Diego, CA · On-site

$171.60K - $302.20K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... At Apple, base pay is one part of our total compensation package and is determined within a range.

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$22K

$96.1K

$129K

How much do soc level 1 jobs pay per year?

As of May 28, 2026, the average yearly pay for soc level 1 in the United States is $96,093.00, according to ZipRecruiter salary data. Most workers in this role earn between $77,500.00 and $109,500.00 per year, depending on experience, location, and employer.

What is a SOC Level 1 job?

A SOC Level 1 job is an entry-level position in a Security Operations Center (SOC) responsible for monitoring security alerts, analyzing potential threats, and escalating incidents as needed. Analysts use security tools like SIEM systems to detect suspicious activity and respond to cyber threats. They also document incidents, follow standard operating procedures, and collaborate with higher-tier analysts for deep investigations. Strong analytical skills, attention to detail, and knowledge of cybersecurity concepts are essential for this role.

What are the key skills and qualifications needed to thrive in the Soc Level 1 position, and why are they important?

To thrive as a SOC Level 1 analyst, you need foundational knowledge of cybersecurity principles, network monitoring, and incident response—usually backed by a degree in IT, computer science, or relevant certifications like CompTIA Security+. Familiarity with Security Information and Event Management (SIEM) tools, ticketing systems, and basic scripting is typically required. Strong attention to detail, analytical thinking, and effective communication skills can help you stand out in this role. These competencies are crucial for quickly identifying and escalating security incidents, ensuring ongoing protection of organizational assets.

What does a typical workday look like for a SOC Level 1 analyst?

As a SOC Level 1 analyst, your day often begins with monitoring security alerts and events across various systems using specialized monitoring tools. You'll spend much of your time investigating suspicious activities, documenting findings, and escalating potential incidents to senior analysts or other IT teams as necessary. Collaboration with colleagues, following established incident response procedures, and maintaining detailed logs are integral parts of the role. While the environment is fast-paced and sometimes high-pressure due to the importance of real-time threat detection, the position provides an excellent foundation for learning and advancing within the cybersecurity field.
More about Soc Level 1 jobs
What cities are hiring for Soc Level 1 jobs? Cities with the most Soc Level 1 job openings:
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Soc Level 1 jobs near you
Infographic showing various Soc Level 1 job openings in the United States as of May 2026, with employment types broken down into 64% Full Time, and 36% Part Time. Highlights an 100% In-person job distribution, with an average salary of $96,093 per year, or $46.2 per hour.
SOC Physical Design Static Timing Analysis Engineer

SOC Physical Design Static Timing Analysis Engineer

Intel Corporation

Phoenix, AZ • On-site

$164.47K - $311.89K/yr

Full-time

Medical, Retirement, PTO

Posted 26 days ago

Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 137 rated electronics manufacturers

Job description

Job Details:
Job Description:
As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.
Key Responsibilities:
  • Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
  • Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
  • Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
  • Define methodologies to produce high-quality timing models and enable efficient physical design execution.
  • Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
  • Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
  • Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
  • Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.

Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum Qualifications
  • Bachelor's degree with 8 +years or master's degree with 6+ years or PhD with 4+ years in Electrical Engineering or Computer Engineering or Computer Science or a related field.
  • 7+ years technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies.
  • 3+ years of experience with the following skills:
  • Strong expertise in timing constraint adaptation, physical design knowledge, and optimization techniques.
  • Proficiency with industry-standard tools for timing analysis, extraction, and physical design.
  • Familiarity with TCL scripting and timing budgeting processes.

Preferred Skills/Experience:
  • Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
  • Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
  • Knowledge of tools, flows, and methodologies for high-performance physical design.
  • Strong communication skills and ability to articulate technical concepts effectively.
  • DFT architecture knowledge is a strong plus

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, California, Santa Clara
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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