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Soc Design Verification Intern Jobs in Texas (NOW HIRING)

Texas Instruments

As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...

Texas Instruments

$16.50 - $21.50/hr

As a Design Verification intern in this group, you will be responsible for: * Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon ...

Intel

Director, SoC Design Engineering

Austin, TX · On-site

$134K - $164K/yr

The Role and Impact We are seeking a highly experienced a Director, SoC Design Engineering, to lead the functional verification efforts for cutting-edge system-on-chip (SoC) designs. In this ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1063 Location: Austin, TX More about this job > Description Design ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$146K/yr

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub ... Drive Design Verification to closure based on defined verification metrics on test plan, functional ...

Superbeo

Design Verification Lead Engineer

Austin, TX · On-site

Job Title : Design Verification Lead Engineer Job location: Austin, TX Job Duration: 3 Months ... SOC Verification experience using ARM Cortex Microcontroller is required. * Experience with ...

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Soc Design Verification Intern information

What does a SoC Design Verification intern do?

A SoC (System on Chip) Design Verification Intern assists in ensuring that integrated circuits function as intended by verifying design specifications through simulation and testing. They typically work with hardware description languages like Verilog or SystemVerilog, develop testbenches, and analyze verification results. Interns collaborate closely with design and verification engineers to debug issues, automate verification processes, and contribute to the overall quality of the SoC design. This role provides hands-on experience in the semiconductor industry and is a great starting point for a career in hardware engineering.

What are the key skills and qualifications needed to thrive as a SoC Design Verification intern?

To thrive as a SoC Design Verification Intern, you need a solid understanding of digital logic design, computer architecture, and familiarity with hardware description languages like Verilog or VHDL, often supported by coursework in electrical or computer engineering. Experience with verification tools such as SystemVerilog, UVM, and simulation environments is typically required. Attention to detail, problem-solving abilities, and strong communication skills help interns effectively identify bugs and collaborate with engineering teams. These skills and qualities are crucial for ensuring high-quality, functional SoC designs that meet rigorous industry standards.

What are some common challenges faced by SoC Design Verification interns and how can they be overcome?

SoC Design Verification Interns often face the challenge of understanding complex system architectures and quickly learning industry-standard verification methodologies such as UVM. Navigating large codebases and identifying sources of bugs can be daunting, especially when working with cross-functional teams. Overcoming these challenges typically involves proactive communication with mentors, thorough documentation review, and hands-on practice with simulation tools. Interns who ask questions and collaborate closely with experienced verification engineers tend to ramp up more efficiently and contribute effectively to project milestones.

What is the difference between Soc Design Verification Intern vs Soc Design Verification Engineer?

AspectSoc Design Verification InternSoc Design Verification Engineer
CredentialsTypically pursuing or recent graduate in Electrical Engineering, Computer Engineering, or related fieldsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; often with industry experience
Work EnvironmentInternship setting, assisting verification teams, learning tools and processesFull-time role, responsible for verification planning, testbench development, and debugging
Industry UsageCommonly used in semiconductor and electronics companies during early career stagesStandard role in chip design companies, responsible for verification of complex SoCs

The main difference is that the Soc Design Verification Intern is an entry-level, temporary position focused on learning and supporting verification tasks, while the Soc Design Verification Engineer is a full-time professional responsible for designing and executing verification plans for SoC projects.

Infographic showing various Soc Design Verification Intern job openings in Texas as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 10% Part Time, and 2% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution.

Senior SoC Design Verification Engineer

Dallas, TX • On-site

Optimalsemi
See more jobs at Optimalsemiexternal

$135K - $164K/yr

Other

Re-posted 8 days ago

Job description

Fiori Technology Solutions is currently hiring for a Design Verification Engineer. This is fulltime permanent position.

We are looking to fill multiple Design Verification openings. We are headquartered in Dallas, USA and have office in Hyderabad, India.

Welcome to a growing team that tests and validates new semiconductor packages. Our exciting IC product lines require thorough and accurate testing to develop detailed wafer maps which identify components that are suitable for production and manufacturing. In this role, you will be a member of a team with an open and collaborative work environment.

Skills and Qualifications Required:
  • Roles requiring both 3+ and 8+ years industry experience.
  • Bachelor’s or Master’s degree in related engineering field.
  • Ability to work independently and across geographies
Specific responsibilities include:
  • Digital verification for complex SoC with MCUs (ARM CM0+/CM3/4/CM33) with complex peripherals, hardware accelerators, memory architectures, bus architectures
  • Familiar with SoC development flow and environments
  • Have experience with mixed signal circuits: ADCs/DACs, OSCs, clock trees, power management circuits together with digital Ips
  • Basic understanding of UVM and testcase development in UVM environment
  • Working experience with mixed simulation environment (Digital + Analog model)
  • Nice to have: Exposure to DPLL/Synthesizer kind of design will make it easier to ramp up.
  • Nice to have: Exposure to cadence simulation tools and debugging (simulation, regression, coverage analysis, GLS)

For more information regarding FTS please visit our website https://fiorit.com. We provide an open door policy; please feel free to follow up by email info@fiorit.com or by phone +91 7416614439 and ask for a Talent Manager to assist you.

India Office Plot No 133, Sri Hari Nilayam,
Vaishali Nagar, Madinaguda,
Hyderabad - 500049

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