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Soc Design Validation Engineer Jobs (NOW HIRING)

SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...

As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...

We are seeking a PCB Design & Validation Engineer to own the design of test/eval boards and lead validation of our high-speed optical transceivers. You will design the PCB platforms that enable ...

You are expected to have excellent understanding of digital design fundamentals, SoC Power trees ... verification engineers to define and execute comprehensive validation plans, identify gap/risk ...

... SoC is functioning per design specs, achieves expected performance and meets industry requirements and standards. Experience in IC and SoC functional validation • Demonstrate expertise in specific ...

Validation Engineer

Roseville, CA · On-site

$65 - $100/hr

... SoC is functioning per design specs, achieves expected performance and meets industry requirements and standards. Experience in IC and SoC functional validation • Demonstrate expertise in specific ...

Validation Engineer

Roseville, CA · On-site

$65 - $100/hr

... SoC is functioning per design specs, achieves expected performance and meets industry requirements and standards. Experience in IC and SoC functional validation • Demonstrate expertise in specific ...

... SoC is functioning per design specs, achieves expected performance and meets industry requirements and standards. Experience in IC and SoC functional validation • Demonstrate expertise in specific ...

... SoC is functioning per design specs, achieves expected performance and meets industry requirements and standards. Experience in IC and SoC functional validation • Demonstrate expertise in specific ...

... SoC is functioning per design specs, achieves expected performance and meets industry requirements and standards. Experience in IC and SoC functional validation • Demonstrate expertise in specific ...

SOC Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

... Design Verification Engineers to join our Data Center SoC Verification team. In this role, you will ... Create directed and constrained-random test scenarios to validate functionality and architectural ...

Electrical Design Validation Engineer Responsibilities: * Define and execute electrical validation methodologies for PCBs and subsystems * Develop and track detailed test plans for modules and top ...

Electrical Design Validation Engineer Responsibilities: * Define and execute electrical validation methodologies for PCBs and subsystems * Develop and track detailed test plans for modules and top ...

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Soc Design Validation Engineer information

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How much do soc design validation engineer jobs pay per hour?

As of Sep 11, 2026, the average hourly pay for soc design validation engineer in the United States is $52.00, according to ZipRecruiter salary data. Most workers in this role earn between $39.42 and $63.22 per hour, depending on experience, location, and employer.

What are popular job titles related to Soc Design Validation Engineer jobs?

For Soc Design Validation Engineer jobs, the most frequently searched job titles are:

SoC Design Engineer

Santa Clara, CA • On-site

OMNIVISION
Software Development • 1 - 5K employees

Full-time

This job post has expired today. Applications are no longer accepted.


Job description

Job Title: SoC Design Engineer
 
Job Duties:
 
  • Design and verify digital circuits for CMOS image sensors (CIS), including sensor array timing control logic, analog-digital interface modules, and ISP (Image Signal Processing) data pipelines, in accordance with product requirements, system architecture, and ASIC design methodology.
  • Perform full-chip SoC integration, including IP integration, clock/reset domain management, power-aware design, and system-level verification to ensure functional correctness and tape-out readiness.
  • Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog/SystemVerilog, simulation, synthesis and DFT implementation.
  • Conduct static timing analysis (STA) for image sensor timing-critical paths, including interfaces between analog front-end and digital control logic, ensuring robust timing closure across process corners.
  • Collaborate closely with the back-end physical design team on floor planning, timing closure, power optimization, and DFT strategy throughout the implementation cycle.
  • Perform pre-silicon verification using UVM-based testbenches, and scripting languages (Python, Perl) for automation, coverage analysis, and regression testing.
  • Work with sensor analog/digital engineers to co-develop system-level architectures, define interface protocols, and validate mixed-signal functionality during integration and bring-up.
  • Partner with algorithm engineers to implement hardware-efficient microarchitectures, develop C/C++ reference models, perform RTL-to-model co-simulation, and optimize hardware/software partitioning for imaging pipelines.
  • Support post-silicon activities including chip bring-up, silicon validation, debugging, and performance tuning in collaboration with firmware, application, and image quality teams.
  • Contribute to image tuning, sensor characterization, and product qualification by analyzing hardware behavior and providing feedback to algorithm and system teams.
  • Create and maintain technical documentation, including architecture specifications, registers, interface control documents. 
 
Requirements:
 
Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a closely related field
 
Require one year experience in digital design.
 
Must have the experience/skills:
 
  • Architecture for Wi-Fi 6 AP transmitter.
  • Wi-Fi PHY based RTL design and verification using Verilog.
  • Module-level verification and full-chip integration support.
  • Design optimization techniques for area, power, and timing.
  • Using industry-standard digital design and verification tools.
 

Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.