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Serdes Verification Engineer Jobs (NOW HIRING)

Engineering Group, Engineering Group > Software Engineering General Summary: ** This position is ... Knowledge of Modem, RF or SERDES high speed interfaces , clock/power management, low-power modes ...

Engineering Group, Engineering Group > Software Engineering General Summary: ** This position is ... Knowledge of Modem, RF or SERDES high speed interfaces , clock/power management, low-power modes ...

Job Area:Engineering Group, Engineering Group > Software EngineeringGeneral Summary:** This ... Knowledge of Modem, RF or SERDES high speed interfaces , clock/power management, low-power modes ...

IC Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

You'll work alongside a team of world-class engineers solving some of the hardest challenges in ... High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification . * UCIe, PCIe/CXL, Ethernet, or ...

MAC Verification

Santa Clara, CA · On-site

$159K/yr

We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Ethernet IP (mac + pcs + serdes) experience. Job is to verify Ethernet ...

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Serdes Verification Engineer information

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$105.5K

$149.2K

$167K

How much do serdes verification engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for serdes verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a serdes verification engineer?

Serdes Verification Engineers are specialized professionals who test and validate Serializer/Deserializer (SerDes) circuits used in high-speed data communication systems. Their main responsibility is to ensure the reliable operation and compliance of SerDes designs, typically found in chips for networking, storage, and computing devices. They use simulation, modeling, and hardware validation techniques, often writing testbenches in languages like SystemVerilog or UVM, to verify that the SerDes interfaces meet performance and functional requirements. These engineers work closely with design teams to identify, report, and debug issues, ensuring the final product operates as intended.

What are the key skills and qualifications needed to thrive as a serdes verification engineer?

To thrive as a Serdes Verification Engineer, you need a solid understanding of high-speed serial interfaces, digital design, and verification methodologies, usually backed by a degree in electrical or computer engineering. Familiarity with HDL languages like Verilog/SystemVerilog, simulation tools (e.g., UVM, VCS, ModelSim), and protocols such as PCIe or Ethernet is typically required. Strong analytical thinking, problem-solving, and effective communication skills help you identify issues and collaborate with design teams. These competencies are crucial for ensuring robust and reliable Serdes interface designs in complex electronic systems.

What are common challenges faced by serdes verification engineers during the verification process?

Serdes Verification Engineers often encounter challenges such as debugging complex high-speed data transmission issues, ensuring thorough coverage of all protocol compliance scenarios, and managing intricate testbenches for mixed-signal environments. Collaboration with design and analog teams is crucial to resolve discrepancies between simulated and real-world behavior. Staying updated on evolving standards and integrating new verification methodologies are also important aspects of the role.

What are popular job titles related to Serdes Verification Engineer jobs?

For Serdes Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Serdes Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Principal Digital Verification Engineer

Pittsford, NY

Ciena
Telecommunications • 5 - 10K employees

$147K - $234K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 10 days ago


Job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We're a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being-on and off the job. Connect with a career that matters.


How You Will Contribute:

The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an expert digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects, in our Rochester NY office.

Your role as an expert digital verification engineer will be to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks, cores, and subsystems for the Wavelogic family of products.Following are examples of responsibilities in this role, however the role is not necessarily limited to this list and can vary from project to project:

  • You will be expected to quickly understand the architecture and functional requirements of the project in order to effectively communicate and collaborate with systems engineers and architects.
  • You will be responsible for the complete and detailed validation of entire subsystems by using an appropriate combination of simulation, formal and coverage methods.
  • You will be responsible for creating, reviewing and optimizing simulation environment components, test case scenarios as well as functional coverage and formal verification test plans.
  • You will be expected, if/when appropriate, to lead focused groups of individuals or mentor individuals and manage their priorities towards reaching a specific set of objectives
  • You will be accountable for estimating schedules, and once approved track them towards timely completion, while providing clear and precise status updates at regular intervals
  • Possibility of reporting directlyto the Senior Manager as an ASIC Verification Prime
    • As an ASIC verification Prime, you would be responsible for all aspects of the verification of the digital portion of the Serdes as well as working with partner teams to ensure overall Serdes coverage.
    • You would also be responsible for participating in architectural and design reviews to proactively advise on verification impacts and improvements for schedule and or coverage.

The Must Haves:

  • Minimum Bachelor's degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with expert level experience in the use of System Verilog, UVM, SVA, and simulators from major vendors.
  • Proven ability in determining appropriate and comprehensive digital verification and coverage strategies
  • Highly motivated self-starter, able to work independently, while being a great teammate
  • Ability to methodically address (debug) sophisticated technical problems.
  • Excellent organization, written and oral English communication skills.

Assets:

  • Experience with
    • Formal verification methods
    • DSP and/or Forward Error Correction
    • Using Jira for bug tracking and GIT for source code management and revision tracking
  • Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.

The annual salary range for this position is $147,100 - $234,900.

#LI-BH #LI-Onsite

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is anEqual Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.