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Serdes Verification Engineer Jobs (NOW HIRING)

TekClap

Signal Verification Engineer

San Jose, CA · On-site

$159K/yr

Develop verification solutions for wireless RF transceivers and high-speed PHY/SerDes designs ... Bachelor's degree in Electrical/Electronics Engineering or related field. * 2+ years of experience ...

InterSources Inc.

Verification Engineer

Saratoga, CA · On-site

$150K/yr

... Engineering, or related field. * Experience: A MINIMUM of 8-15 years in ASIC verification in the ... Serdes is a strong plus. * Communication Skills: Exceptional communication abilities, capable of ...

Embtel Inc

Verification Engineer (Remote)

Campbell, CA · On-site

$157K/yr

Staff Verification Engineer Office Located in Campbell, CA ( 100 % remote considered) Duration ... Prior experience with VIP of multi-protocol Serdes Prior experience with Protocol verification such ...

Pic-Time Ltd.

Verification Engineer

Denver, CO · On-site

$130K - $200K/yr

We are looking for a talented Design Verification Engineer to join our VLSI team. What you will be ... Experience validating RF Comms, DSP Algorithms, and High Speed SERDES * Experience validating ...

idexcel

SoC Verification Engineer

San Jose, CA · On-site

$159K/yr

Understanding of ONFI, NVMe and SERDES a major plus. Qualifications Candidate must have 7+ years of experience in Verification . Must have experience in Verification methodology like UVM, OVM, VMM ...

Ericsson GmbH

IP Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Senior Design Verification Engineer -- ASIC IP Silicon Verification | 5G Infrastructure | Austin ... Familiarity with SerDes, PCIe, ARM subsystems, DSP/accelerators, or Ethernet. * Proficiency in TCL ...

Embtel Inc

Senior Verification Engineer (Remote)

Campbell, CA · On-site

$157K/yr

Senior Verification Engineer Location: Campbell, CA ( 100 % remote considered) Duration: Full Time ... Prior experience with VIP of multi-protocol Serdes. * Prior experience with Protocol verification ...

Lumilens Inc.

Verification Engineer

San Jose, CA · On-site

$159K/yr

You'll work alongside a team of world-class engineers solving some of the hardest challenges in ... High‑speed SerDes, PAM4, or FEC/coding (Reed‑Solomon) verification . * UCIe, PCIe/CXL, Ethernet ...

Eridu Corporation

Verification Engineer

Saratoga, CA · On-site

$150K/yr

... Engineering, or related field. * Experience: A MINIMUM of 8-15 years in ASIC verification in the ... Serdes is a strong plus. * Communication Skills: Exceptional communication abilities, capable of ...

Eridu AI

Verification Engineer

Saratoga, CA · On-site

$195K - $265K/yr

... Engineering, or related field. * Experience: A MINIMUM of 8-15 years in ASIC verification in the ... Serdes is a strong plus. * Communication Skills: Exceptional communication abilities, capable of ...

Saigepartners

AMD/DMS Verification Engineer

San Jose, CA · On-site

$159K/yr

AMS/DMS Verification Engineer Position Overview We are seeking an AMS/DMS Verification Engineer to ... Experience with SerDes and high-speed PHY technologies. * Experience supporting silicon bring-up ...

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Serdes Verification Engineer information

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$105.5K

$149.2K

$167K

How much do serdes verification engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for serdes verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a serdes verification engineer?

Serdes Verification Engineers are specialized professionals who test and validate Serializer/Deserializer (SerDes) circuits used in high-speed data communication systems. Their main responsibility is to ensure the reliable operation and compliance of SerDes designs, typically found in chips for networking, storage, and computing devices. They use simulation, modeling, and hardware validation techniques, often writing testbenches in languages like SystemVerilog or UVM, to verify that the SerDes interfaces meet performance and functional requirements. These engineers work closely with design teams to identify, report, and debug issues, ensuring the final product operates as intended.

What are the key skills and qualifications needed to thrive as a serdes verification engineer?

To thrive as a Serdes Verification Engineer, you need a solid understanding of high-speed serial interfaces, digital design, and verification methodologies, usually backed by a degree in electrical or computer engineering. Familiarity with HDL languages like Verilog/SystemVerilog, simulation tools (e.g., UVM, VCS, ModelSim), and protocols such as PCIe or Ethernet is typically required. Strong analytical thinking, problem-solving, and effective communication skills help you identify issues and collaborate with design teams. These competencies are crucial for ensuring robust and reliable Serdes interface designs in complex electronic systems.

What are common challenges faced by serdes verification engineers during the verification process?

Serdes Verification Engineers often encounter challenges such as debugging complex high-speed data transmission issues, ensuring thorough coverage of all protocol compliance scenarios, and managing intricate testbenches for mixed-signal environments. Collaboration with design and analog teams is crucial to resolve discrepancies between simulated and real-world behavior. Staying updated on evolving standards and integrating new verification methodologies are also important aspects of the role.

What are popular job titles related to Serdes Verification Engineer jobs?

For Serdes Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Serdes Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Principal Design Verification Engineer- SerDes/PHY IP

San Jose, CA • On-site

Astera Labs
Semiconductor and Electronic Component Manufacturing • 11 - 50 employees
Learn more about Astera Labsexternal

$207K - $230K/yr

Full-time

Posted 10 days ago

Job description

Role Overview

Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP - the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.

This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story. You'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.

Key Responsibilities

  • Verification Architecture & Strategy

    • Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers
    • Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks
    • Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows

  • Execution & Coverage Closure

    • Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes
    • Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios
    • Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out

  • Physical Layer & Protocol Verification

    • Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards
    • Model and validate channel behavior, link training state machines, and analog handoff scenarios
    • Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks

  • Cross-Functional Leadership

    • Mentor junior DV engineers and set technical direction across the verification team
    • Collaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams
    • Contribute to verification IP reuse strategy and tooling improvements across product lines
Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
  • Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
  • Expert-level proficiency in SystemVerilog and UVM
  • Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
  • Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL
Preferred Qualifications
  • MS or PhD in Electrical Engineering or Computer Engineering
  • Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
  • Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
  • Scripting proficiency in Python or Perl for verification automation and regression management
  • Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results
  • Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment

Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

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