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Serdes Test Engineer Jobs (NOW HIRING)

Broadcom, Inc.

ATE Test Development Engineer

Irvine, CA · On-site

$108K - $172K/yr

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed SERDES (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Broadcom

ATE Test Development Engineer

Irvine, CA · On-site

$108K - $172K/yr

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed SERDES (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Broadcom, Inc.

ATE Test Development Engineer

Irvine, CA · On-site

$108K - $172K/yr

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed SERDES (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Broadcom

ATE Test Development Engineer

Irvine, CA

$108K - $172K/yr

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed SERDES (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Apple

SerDes System Validation Engineer

Austin, TX

This will involve a SerDes bring up in system environment, verifying basic operations, analyzing ... Be involved in mixed-signal verification tasks to assure Pre Silicon test coverage and robustness.

Apple

SerDes Micro Architect

San Diego, CA · On-site

The SERDES IPs will be used in Apple silicon offering breakthrough power and performance for iPhone ... bring up and factory test. You will work with signal integrity engineers to determine system ...

Apple

SerDes System Validation Engineer

Austin, TX

This will involve a SerDes bring up in system environment, verifying basic operations, analyzing ... Be involved in mixed-signal verification tasks to assure Pre Silicon test coverage and robustness.

Qualcomm

Staff Bench Test Engineer

Santa Clara, CA · On-site

$151K - $227K/yr

The Post Silicon Engineering group in the Qualcomm Connectivity & Networking division develops test ... SERDES Interfaces such as PCIe, USB3, MIPI (DSI, CSI), leading edge LP-DDR & PC-DDR Subsystem ...

Broadcom, Inc.

DFT Engineer

San Jose, CA · On-site

$120K - $192K/yr

... SerDes and other I/P DFT integration * Pattern generation and verification at chip level, rapid bring-up at ATE and RMA support * Working closely with STA and DI Engineers design closure for test

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How much do serdes test engineer jobs pay per hour?

As of Jun 7, 2026, the average hourly pay for serdes test engineer in the United States is $59.03, according to ZipRecruiter salary data. Most workers in this role earn between $44.71 and $75.96 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Serdes Test Engineer, and why are they important?

To thrive as a Serdes Test Engineer, you need a solid background in electrical engineering, signal integrity, and high-speed digital design, often supported by a relevant degree. Proficiency with oscilloscopes, bit error rate testers (BERTs), lab automation software, and familiarity with industry standards like PCIe or Ethernet is typically required. Strong problem-solving, attention to detail, and effective communication skills help you diagnose issues and collaborate with cross-functional teams. These competencies ensure accurate validation of Serdes interfaces, which is vital for reliable high-speed data transmission in modern electronic systems.

What are some typical challenges faced by Serdes Test Engineers during validation and how are they addressed?

Serdes Test Engineers often encounter challenges such as signal integrity issues, jitter, and crosstalk when validating high-speed serial interfaces. Addressing these requires a deep understanding of test equipment, careful setup of test environments, and collaboration with design and layout teams to troubleshoot root causes. Engineers frequently use oscilloscopes, BERTs, and protocol analyzers to capture and analyze signal anomalies, and may need to adjust test methodologies or recommend design changes to meet compliance standards.

What is a Serdes Test Engineer?

A Serdes Test Engineer is a professional who specializes in testing serializer/deserializer (SerDes) components used in high-speed data communication interfaces. Their responsibilities typically include developing and executing test plans, validating signal integrity, debugging hardware and firmware issues, and ensuring compliance with industry standards. They work closely with design and validation teams to identify and resolve performance or reliability issues in SerDes circuits. This role requires strong knowledge of high-speed digital electronics, test equipment, and protocols such as PCIe, Ethernet, or USB.
Infographic showing various Serdes Test Engineer job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 95% Full Time, 1% Part Time, and 3% Contract. Highlights an 87% Physical, 8% Hybrid, and 5% Remote job distribution, with an average salary of $122,773 per year, or $59 per hour.
Principal Engineer, SerDes Validation

Principal Engineer, SerDes Validation

Ayar Labs

San Jose, CA • On-site

$180K - $230K/yr

Full-time

Posted 17 days ago

Job description

Principal Engineer, SerDes Validation
Location: San Jose (on-site)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
We are seeking a System validation expert to spearhead the validation efforts that ensure our groundbreaking products meet and exceed both component and system-level requirements. This pivotal role will drive the transition of our technology from initial release to customer deployment, guaranteeing a seamless and high-performance experience for our clients.
If you are a seasoned validation expert who thrives on solving complex technical problems and is passionate about delivering high-quality products, we invite you to apply and join our team of innovators. Ayar Labs is pushing the boundaries of optical interconnect technology with our revolutionary multi-wavelength sources and CMOS chiplets.
Essential Functions:
  • Lead Validation Strategy: Define and implement comprehensive validation methodologies that guarantee high-speed performance of our optical chiplets, both at component and system-level. This includes developing test plans, defining success criteria, and selecting appropriate test equipment and methodologies.
  • Drive Product Bring-up: Collaborate with Design Engineering to bring up cutting-edge silicon photonic and laser products, troubleshooting and resolving complex technical issues on the optical SerDes devices.
  • Validate Component and System Performance: Perform rigorous design validation on new chips and products through high-speed characterization of electro-optic systems using signal integrity (SI) and eye analysis techniques.
  • Lead New Product Introduction (NPI): Collaborate with multi-disciplinary teams to identify and implement product improvements through bench characterization and ensure successful transition of products from development to mass production.
  • Deliver Customer-Ready Documentation: Author and maintain comprehensive customer-facing validation reports and documentation that clearly communicate product performance and reliability.
  • Develop Test Software and Infrastructure: Create and maintain software scripts and test hardware stations required for efficient and comprehensive validation.

Basic Qualifications:
  • Master's degree in Electrical Engineering or equivalent
  • 10+ years of experience with component and system test equipment (BERT, DCA, OSA, etc.) and standard signal quality metrics (TDECQ, SRS, URS).
  • 5+ years of experience in programming languages (Python, etc.) for test automation and data analysis.
  • Deep understanding of communication protocols and standards (Ethernet, PCIe, etc.).
  • Proven ability to analyze complex technical problems, identify root causes, and develop effective solutions.
  • Understanding of data analysis, process control, and statistical methods.
  • Experience with SoC validation planning, bring-up, debugging, and optimization.
  • Experience with high-speed SerDes and their characterization and optimization.

Preferred Qualifications:
  • Ph.D. in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
  • 5+ years of hands-on experience in semiconductor laser & photonic device validation.
  • Working knowledge of optical transceiver packaging and integration challenges.
  • Strong project management and communication skills.

Salary range: $180,000 - $230,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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