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Senior Signal Integrity Engineer Jobs in Texas (NOW HIRING)

Senior Signal Integrity Engineer

Austin, TX · On-site

$165K/yr

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute ...

Senior Signal Integrity Engineer

Austin, TX · Hybrid

$165K/yr

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute ...

Signal Integrity Engineer Locations: On-site in Richardson, TX or San Jose, CA Type: Permanent / Full-time Compensation: Competitive and commensurate with experience (multiple openings available ...

Signal Integrity Engineer

Richardson, TX · On-site

$151K/yr

Signal Integrity Engineer Locations: On-site in Richardson, TX or San Jose, CA Type: Permanent / Full-time Compensation: Competitive and commensurate with experience (multiple openings available ...

Signal Integrity Engineer

Austin, TX · On-site

$100K - $500K/yr

Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade ...

... signal and power integrity • Work with product engineering and system engineering to debug and to improve product yield Minimum Qualifications Minimum requirement of a bachelors degree Preferred ...

We are now looking for a Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market ...

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Senior Signal Integrity Engineer information

See Texas salary details

$55.4K

$117.9K

$171K

How much do senior signal integrity engineer jobs pay per year?

As of Jul 29, 2026, the average yearly pay for senior signal integrity engineer in Texas is $117,907.00, according to ZipRecruiter salary data. Most workers in this role earn between $97,400.00 and $133,700.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Senior Signal Integrity Engineer position, and why are they important?

To excel as a Senior Signal Integrity Engineer, a thorough understanding of high-speed digital and analog circuit design, electromagnetic compatibility, and signal integrity analysis is required, typically supported by a degree in electrical engineering or a related field. Familiarity with industry tools such as Ansys HFSS, Keysight ADS, HyperLynx, and relevant simulation or measurement equipment is essential, along with certifications like IPC or IEEE being a plus. Strong problem-solving skills, attention to detail, and effective cross-functional communication set top candidates apart. These abilities ensure the accurate design and troubleshooting of complex electronic systems, which are critical for product performance and reliability.

What are some common challenges faced by Senior Signal Integrity Engineers in their daily work?

Senior Signal Integrity Engineers often deal with complex issues such as mitigating signal degradation in high-speed circuits, balancing trade-offs between performance, cost, and manufacturability, and staying ahead of the latest industry standards. Their daily work typically involves analyzing schematic and PCB layouts, collaborating closely with hardware, PCB, and test teams, and validating designs through simulation and lab measurement. Navigating competing requirements from various engineering disciplines can be challenging, requiring strong negotiation and problem-solving skills. These challenges make the role both demanding and rewarding, offering continual learning opportunities and the chance to play a critical part in developing innovative electronics.

What does a Senior Signal Integrity Engineer do?

A Senior Signal Integrity Engineer is responsible for ensuring the integrity of high-speed signals in electronic systems, minimizing issues like crosstalk, reflections, and electromagnetic interference. They analyze and optimize PCB layouts, interconnects, and transmission lines using simulation tools and measurement techniques. Their work involves collaboration with hardware design, PCB layout, and manufacturing teams to improve signal performance and reliability. Additionally, they troubleshoot high-speed signal issues and contribute to the development of best practices for high-frequency electronic designs.

What are the most commonly searched types of Signal Integrity Engineer jobs in Texas? The most popular types of Signal Integrity Engineer jobs in Texas are:
What job categories do people searching Senior Signal Integrity Engineer jobs in Texas look for? The top searched job categories for Senior Signal Integrity Engineer jobs in Texas are:
What cities in Texas are hiring for Senior Signal Integrity Engineer jobs? Cities in Texas with the most Senior Signal Integrity Engineer job openings:
Infographic showing various Senior Signal Integrity Engineer job openings in Texas as of July 2026, with employment types broken down into 94% Full Time, 3% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $117,907 per year, or $56.7 per hour.

Senior Signal Integrity Engineer

Graphcore

Austin, TX • On-site

$165K/yr

Full-time

Medical, Dental, Vision, Life, Retirement

Re-posted 13 days ago


Job description

1671
About the Role
We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design, with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication.
Key Responsibilities
  • End-to-end signal integrity analysis for blade- and rack-level system architectures.
  • Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, I2C, etc. and related interconnects.
  • Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE, or similar.
  • Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes.
  • Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology.
  • Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance.
  • Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions.
  • Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware.
  • Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders.

Required Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Strong experience in signal integrity for high-speed digital systems.
  • Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes.
  • Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and crosstalk.
  • Knowledge of high-speed interfaces such as PCIe Gen4/5/6, Ethernet, DDR, SerDes, and related I/O technologies.
  • Experience with SI/PI simulation tools such as HFSS, ADS, Sigrity, CST, SPICE, or equivalent.
  • Ability to correlate lab measurements with simulations and use data to guide design decisions.
  • Strong communication skills, including the ability to produce clear validation reports, present technical findings, and work effectively across multi-functional engineering teams.

Preferred Qualifications
  • Experience in hyperscale, data center, cloud infrastructure, or advanced compute hardware environments.
  • Experience with blade, backplane, board-to-board, cable, or rack-level interconnect architectures.
  • Knowledge of thermal and mechanical considerations that impact SI/PI performance.
  • Experience with calibration, de-embedding, fixture design, lab automation, or measurement methodology development.
  • Experience using Python, MATLAB, or similar scripting languages for simulation automation, measurement automation, and data analysis.

Tools / Technologies
Measurement: VNA, TDR, BERT, high-speed oscilloscopes
Simulation: Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE
Interfaces: PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, high-speed interconnects
Analysis: S-parameters, eye diagrams, jitter, timing margins, impedance control, crosstalk, insertion loss, return loss, de-embedding, measurement-to-simulation correlation
Why Join Us
This is an opportunity to work on complex, high-performance compute platforms while partnering with experienced technical leaders, ODMs, and interconnect vendors. You will play a key role in defining, measuring, validating, and optimizing next-generation system-level I/O performance.
USA Benefits
In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.