About the role SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems. You will work ...
About the role SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems. You will work ...
Senior Hardware Design Engineer
Austin, TX · On-site
About the role SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems. You will work ...
Senior Hardware Design Engineer
Austin, TX · On-site
About the role SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems. You will work ...
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Apple products might even be one of the reasons you wanted to BE a Hardware Design Engineer. Now, imagine yourself designing future Apple products. The iPhone team is looking for engineers who are ...
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Senior Hardware Design Engineer information
See Georgetown, TX salary details
$85.9K - $93.8K
3% of jobs
$93.8K - $101.7K
7% of jobs
$101.7K - $109.5K
11% of jobs
$111.6K is the 25th percentile. Wages below this are outliers.
$109.5K - $117.4K
15% of jobs
The median wage is $124.9K / yr.
$117.4K - $125.2K
15% of jobs
$125.2K - $133.1K
14% of jobs
$139.3K is the 75th percentile. Wages above this are outliers.
$133.1K - $140.9K
14% of jobs
$140.9K - $148.8K
8% of jobs
$148.8K - $156.6K
5% of jobs
$156.6K - $164.5K
5% of jobs
$164.5K - $172.4K
3% of jobs
$85.9K
$129.2K
$172.4K
How much do senior hardware design engineer jobs pay per year?
What is a senior hardware design engineer?
What are the key skills and qualifications needed to thrive as a senior hardware design engineer?
How do senior hardware design engineers typically collaborate with cross-functional teams during a project?
What is the difference between Senior Hardware Design Engineer vs Hardware Design Engineer?
| Aspect | Senior Hardware Design Engineer | Hardware Design Engineer |
|---|---|---|
| Qualifications | Bachelor's or Master's in Electrical Engineering or related field; 5+ years experience | Bachelor's degree in Electrical Engineering or related field; 1-3 years experience |
| Responsibilities | Leading complex hardware projects, mentoring junior engineers, system architecture | Designing and testing hardware components, supporting project development |
| Work Environment | Design teams, R&D departments, collaborative projects | Design labs, development teams, manufacturing support |
The main difference is experience level and responsibility. Senior Hardware Design Engineers lead projects and mentor others, while Hardware Design Engineers focus on designing hardware components. Both roles require similar technical skills but differ in scope and leadership expectations.
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Full-time
Posted 10 days ago
Job description
The hardware design team writes the RTL for SambaNova's RDU, the processor behind our AI workload acceleration systems, covering the compute, memory, and networking subsystems. Engineers own specific blocks inside a larger subsystem, working alongside the principal engineers and architects who set its direction. A block stays with the engineer who wrote it through PPA closure, tapeout, and bring-up, so you debug your own design in silicon.
SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems. You will work alongside principal engineers, architects, design verification engineers, and physical design engineers to implement innovative features in hardware that provide unique value to SambaNova.
In this role you will take ownership of blocks within a larger subsystem - contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tapeout, and silicon bring-up. You will grow your scope over time as you build depth in our architecture.
This role is onsite, based in either our San Jose, CA or Austin, TX office.
ResponsibilitiesSome of your responsibilities will include...
- Work with principal engineers and architects to author sections of the microarchitecture specification for compute, memory, or networking subsystems.
- Code, integrate, and debug SystemVerilog RTL for assigned blocks through the chip implementation and production lifecycle.
- Meet Power, Performance, and Area (PPA) targets for your blocks using advanced digital design techniques for high-speed design.
- Partner with design verification and physical design engineers to converge on functionality, timing, and area.
- Implement SystemVerilog Assertions (SVA) and run lint, CDC, and LEC flows to check design intent and keep blocks clean.
- Participate in design reviews, presenting your design decisions and incorporating feedback.
- Support post-silicon bring-up and debug for the blocks you own.
- Contribute to design flow improvements, including AI and automation in EDA tool methodologies.
- Master's degree in Computer Engineering or Electrical Engineering with 3-5 years of relevant experience, or Bachelor's degree with 5-7 years.
- Solid foundation in computer architecture and digital logic design.
- Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs.
- Experience making design decisions that trade off Power, Performance, and Area (PPA).
- Working knowledge of industry-standard interconnects and protocols (e.g., AXI, PCIe, Ethernet, HBM/DDR).
- Experience with digital logic synthesis tools and Static Timing Analysis (STA).
- Proficiency with industry-standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).
- Experience implementing SystemVerilog Assertions (SVA) to check design intent.
- Familiarity with tools and simulators for hardware performance analysis and tuning.
- Familiarity with Git for managing release cycles.
- Scripting skills in Python and Linux shell.
- Ability to work onsite in San Jose, CA or Austin, TX.
- Exposure to a full ASIC development cycle through tapeout and production silicon.
- Interest in or knowledge of AI workload acceleration techniques.
- Experience with low-power design techniques (clock gating, DVFS) at advanced process nodes.
- Exposure to emulation or FPGA prototyping platforms for pre-silicon validation.