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Senior Brain Machine Interface Jobs (NOW HIRING)

Neuralink

IACUC Administrator

Austin, TX

This role ensures the ethical and regulatory compliance of all animal research activities supporting the development of Neuralink's brain-machine interfaces. Responsibilities include: * Provide ...

Curtiss-Wright

Sr. Electrical Engineer

Aston, PA · On-site

$115K - $130K/yr

Senior Electrical Engineer As a Senior Electrical Engineer, you will be responsible for the design ... Designing and developing electronic controllers and human-machine interfaces * Guiding next ...

Curtiss-Wright

Sr. Electrical Engineer

Aston, PA · On-site

$115K - $130K/yr

Senior Electrical Engineer As a Senior Electrical Engineer, you will be responsible for the design ... Designing and developing electronic controllers and human-machine interfaces * Guiding next ...

Neuralink

IACUC Administrator

Austin, TX · On-site

$26.92 - $44.71/hr

This role ensures the ethical and regulatory compliance of all animal research activities supporting the development of Neuralink's brain-machine interfaces. Responsibilities include: * Provide ...

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Senior Brain Machine Interface information

What is the difference between Senior Brain Machine Interface vs Brain Machine Interface Engineer?

AspectSenior Brain Machine InterfaceBrain Machine Interface Engineer
Required CredentialsMaster's or PhD in neuroscience, biomedical engineering, or related field; extensive experienceBachelor's or Master's in engineering, neuroscience, or related; some experience
Work EnvironmentResearch labs, universities, biotech companiesResearch and development teams, startups, tech companies
Industry UsageAdvanced research, leadership roles, project oversightDesign, develop, and test BCI systems, prototype work

While both roles focus on brain-machine interfaces, the Senior Brain Machine Interface typically involves leadership, advanced research, and strategic oversight, requiring higher credentials and experience. The Brain Machine Interface Engineer is more hands-on, focusing on designing and developing BCI systems, often with less seniority and experience requirements.

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Infographic showing various Senior Brain Machine Interface job openings in the United States as of May 2026, with employment types broken down into 67% Full Time, and 33% Nights. Highlights an 100% In-person job distribution.
Physical Design and Verification Engineer

Physical Design and Verification Engineer

Neuralink

Fremont, CA • On-site

$158K - $243K/yr

Full-time

Medical, Dental, Vision, Retirement

Posted 14 days ago

Job description

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Responsibilities and Description: The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. Required Qualifications:
  • Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
  • Minimum 5 years of experience in digital physical design and verification.
  • Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff.
  • Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification.
  • Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
  • Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools.
  • Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell.
Preferred Qualifications:
  • Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience.
  • Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below.
  • Experience in DFT (Design For Test) flows and ATPG.
  • Experience in I/O design flow in multi-voltage power domain.
  • Experience in building chip floor-plan including pin placement, partitions and power grid.
  • Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints.
  • Experience with build tools such as CMake and Bazel.
  • Experience with code coverage and regression setup.
Expected Compensation: The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees' success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees. Base Salary Range: $158,000-$243,000 USD What We Offer: Full-time employees are eligible for the following benefits listed below.
  • An opportunity to change the world and work with some of the smartest and most talented experts from different fields
  • Growth potential; we rapidly advance team members who have an outsized impact
  • Excellent medical, dental, and vision insurance through a PPO plan
  • Paid holidays
  • Commuter benefits
  • Meals provided
  • Equity (RSUs) *Temporary Employees & Interns excluded
  • 401(k) plan *Interns initially excluded until they work 1,000 hours
  • Parental leave *Temporary Employees & Interns excluded
  • Flexible time off *Temporary Employees & Interns excluded

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