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Senior Brain Machine Interface Jobs in Austin, TX

Neuralink

Digital IC Design Engineer

Austin, TX · On-site

$134K/yr

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface ...

Neuralink

Digital IC Design Engineer

Austin, TX · On-site

$116K - $233K/yr

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface ...

Neuralink

Machine Learning Engineer

Austin, TX · On-site

Engineers on the BCI team utilize signal processing and machine learning to communicate with the brain. You will have access to the most cutting-edge neural interface hardware and develop ...

Neuralink

Machine Learning Engineer

Austin, TX · On-site

$199K - $331K/yr

We are creating devices that enable a bi-directional interface with the brain. These devices allow ... About the Role: Engineers on the BCI team utilize signal processing and machine learning to ...

Neuralink

UI Design Engineer

Austin, TX · On-site

$135K - $281K/yr

We are creating devices that enable a bi-directional interface with the brain. These devices allow ... Our team spans a wide range of disciplines, from neuroscience and machine learning to software ...

Neuralink

Neuroengineer, Next Gen

Austin, TX · On-site

... brain-computer interfaces. We are laying the groundwork for intuitive, high-dimensional, and bidirectional interfaces between brains and machines, with the goal of helping people challenged by a ...

Neuralink

Neuroengineer, Next Gen

Austin, TX · On-site

$122K - $226K/yr

... brain-computer interfaces. We are laying the groundwork for intuitive, high-dimensional, and bidirectional interfaces between brains and machines, with the goal of helping people challenged by a ...

Neuralink

Software Engineer, BCI Applications

Austin, TX · On-site

$150K - $281K/yr

Team Description: The Brain Computer Interface (BCI) Applications Team is responsible for ... The team is hiring software engineers at all levels, both junior and senior. What matters most is ...

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Senior Brain Machine Interface information

What is the difference between Senior Brain Machine Interface vs Brain Machine Interface Engineer?

AspectSenior Brain Machine InterfaceBrain Machine Interface Engineer
Required CredentialsMaster's or PhD in neuroscience, biomedical engineering, or related field; extensive experienceBachelor's or Master's in engineering, neuroscience, or related; some experience
Work EnvironmentResearch labs, universities, biotech companiesResearch and development teams, startups, tech companies
Industry UsageAdvanced research, leadership roles, project oversightDesign, develop, and test BCI systems, prototype work

While both roles focus on brain-machine interfaces, the Senior Brain Machine Interface typically involves leadership, advanced research, and strategic oversight, requiring higher credentials and experience. The Brain Machine Interface Engineer is more hands-on, focusing on designing and developing BCI systems, often with less seniority and experience requirements.

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Senior Brain Machine Interface jobs near you

Hardware/ Software Co-Design Engineer

Neuralink

Austin, TX • On-site

Full-time

Re-posted 8 days ago

Job description

Team Description: 

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. 

Job Description & Responsibilities: 

Our Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

  • Micro-architecture design and RTL implementation of: 
    • Low-power digital signal processors
    • Low-power general-purpose hardware accelerators
    • Low-power graphics processing units
    • Low-power radio MAC/PHY
    • Low-power serial link MAC/PHY
  • Design and optimization of hardware/software interface with firmware engineers
  • Application-specific architecture optimization including:
    • Complex system modeling for energy and performance benchmarks
    • Workload analysis and modeling
    • Energy/performance profiling and analysis
    • Leveraging architecture-level design trade-offs with process technology and workload type
    • Balancing cost and performance under manufacturing process variation 
  • Collaboration on silicon bring-up tests with verification engineers 

Required Qualifications:

  • Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
  • Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
  • Experience designing and implementing embedded software in C or Rust
  • Expertise in SystemVerilog, C/C++, Python
  • Experience designing and implementing  emulation models, transactors, and test environments to replicate hardware behavior
  • Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
  • Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications: 

  • Experience in architecture optimization with process technology customization
  • Experience in the verification of complex digital systems, using industry standard tools
  • Experience in the physical design of complex digital systems, using industry standard tools
  • Experience testing and debugging digital system-on-a-chips
  • Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
  • Experience automating tool flows
  • Experience in processor instruction set architecture design
  • Experience in compiler back-end design and customization

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