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Senior Analog Layout Engineer Jobs in Seattle, WA

Microsoft

Senior Quantum Analog Layout Engineer

Redmond, WA · On-site

$123K - $165K/yr

As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum analog infrastructure, driving Analog ...

IonQ

Senior Mask Layout Engineer

Bothell, WA · On-site

$126K - $166K/yr

As a Senior Mask Layout Engineer, you'll be part of a cross-functional team whose mission is to ... Familiarity with photonic and/or analog electronic device principles including design, test, and ...

SpaceX

RFIC Layout Designer (RFIC Engineering)

Redmond, WA · On-site

$120K - $175K/yr

... engineer to determine pad locations * Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation * Perform layout of custom RF and analog ...

Blue Origin LLC

Senior PCB Layout Engineer

Seattle, WA · On-site

$213.33 - $298.66/hr

## Senior PCB Layout EngineerApplylocations: Greater Seattle Area: Bay Area, CAtime type: Full ... Develop PCB layouts for Digital/Analog/RF circuits with careful attention to impedance control ...

Amazon

PCB Layout Engineer, Amazon Leo

Redmond, WA · On-site

PREFERRED QUALIFICATIONS - 7+ years of analog or RF layout design experience - Experience in design for Aerospace Class 3 - Experience as a technical lead for small teams of PCB layout engineers ...

Blue Origin

Senior PCB Layout Engineer

Seattle, WA · On-site

$197K - $276K/yr

Develop PCB layouts for Digital/Analog/RF circuits with careful attention to impedance control ... Collaborate with electrical engineers on component selection, schematic review, and design ...

Amazon

Sr PCB Layout Engineer, Amazon Leo

Redmond, WA · On-site

As a Sr PCB Layout Engineer, you will participate in the definition and implementation of multiple spacecraft subsystems. You will contribute in all phases of PCB design and production. You must ...

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Senior Analog Layout Engineer information

See Seattle, WA salary details

$67.7K

$144K

$208.8K

How much do senior analog layout engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for senior analog layout engineer in Seattle, WA is $144,025.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,900.00 and $163,300.00 per year, depending on experience, location, and employer.

What is a senior analog layout engineer?

Senior Analog Layout Engineers are experienced professionals who design and implement the physical layout of analog integrated circuits (ICs) such as amplifiers, data converters, and power management chips. They translate circuit schematics into detailed layouts that ensure optimal electrical performance, reliability, and manufacturability. Their responsibilities include working closely with circuit designers, performing layout-versus-schematic (LVS) checks, and using specialized Electronic Design Automation (EDA) tools. Senior engineers often mentor junior staff and help resolve complex layout challenges. Their expertise is critical in ensuring the final chip meets specifications and industry standards.

What are the key skills and qualifications needed to thrive as a senior analog layout engineer?

To thrive as a Senior Analog Layout Engineer, you need deep knowledge of analog/mixed-signal IC layout, semiconductor device physics, and experience with advanced CMOS processes, typically supported by a relevant engineering degree. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and DRC/LVS verification systems is essential. Attention to detail, problem-solving, and strong collaboration skills set standout professionals apart in this role. These abilities ensure high-performance, reliable chip designs that meet stringent industry standards and project timelines.

What are some common challenges senior analog layout engineers face when collaborating with circuit designers, and how can they be addressed?

Senior Analog Layout Engineers often encounter challenges such as translating complex circuit schematics into efficient physical layouts while meeting stringent performance requirements. Miscommunications or differing priorities between layout engineers and circuit designers can lead to design iterations or delays. To address these challenges, it’s important to establish clear communication channels, participate in regular design reviews, and use collaborative tools for feedback and issue tracking. Being proactive in discussing layout constraints and providing early feedback can help ensure that both layout and performance goals are achieved efficiently.

What is the difference between Senior Analog Layout Engineer vs Analog IC Design Engineer?

AspectSenior Analog Layout EngineerAnalog IC Design Engineer
Primary FocusPhysical layout and implementation of analog circuitsDesign and simulation of analog circuits
Skills RequiredLayout tools, fabrication process knowledge, circuit understandingCircuit theory, schematic design, simulation skills
Work EnvironmentFoundries, semiconductor companies, R&D labsDesign teams, R&D departments, EDA tool usage
Common UsageInvolved in physical design phaseInvolved in circuit conceptualization and schematic design

While both roles require a strong understanding of analog circuits, the Senior Analog Layout Engineer focuses on translating circuit schematics into physical layouts, ensuring manufacturability and performance. In contrast, the Analog IC Design Engineer primarily designs and simulates the circuits themselves. Both roles often collaborate but differ in their core responsibilities and skill sets.

What are the most commonly searched types of Analog Layout Engineer jobs in Seattle, WA?

The most popular types of Analog Layout Engineer jobs in Seattle, WA are:

What are popular job titles related to Senior Analog Layout Engineer jobs in Seattle, WA?

For Senior Analog Layout Engineer jobs in Seattle, WA, the most frequently searched job titles are:

What job categories do people searching Senior Analog Layout Engineer jobs in Seattle, WA look for?

The top searched job categories for Senior Analog Layout Engineer jobs in Seattle, WA are:

Senior Analog Layout Engineer jobs near you

Senior Quantum Analog Layout Engineer

Microsoft

Redmond, WA • On-site

$123K - $165K/yr

Full-time

Re-posted 10 days ago

Microsoft rating

8.5

Company rating: 8.5 out of 10

Based on 132 frontline employees who took The Breakroom Quiz

79th of 245 rated software companies

Job description

Overview
Microsoft's Quantum team is building the first scalable, fault-tolerant quantum computer, advancing everything from quantum hardware and error correction to Azure integration. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. As quantum computing enters a pivotal phase of accelerated growth, this position offers a unique opportunity to contribute meaningfully to a transformative technology, such as the Application Specific Integrated Circuits (ASICs) and analog circuitry developed by this team.
As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum analog infrastructure, driving Analog Layout designs and coordinating employees, contingent staff, and external vendors to deliver high-quality designs.
Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
  • Deliver Schematic-to-Graphic Database System (GDS) layouts for cutting-edge, high-performance, high-speed, low-power IP designs, including interconnectivity solutions and foundational Analog circuit blocks. Execute these layouts across multiple process nodes, including deep Fin Field-Effect Transistor (FinFET), following industry best practices.
  • Develop plans for Analog Mask Layout execution and follow processes and methodologies to deliver IP blocks. Coordinate tasks with junior layout team members as needed.
  • Using Cadence Virtuoso (or other equivalent) design tools and flows; perform layout implementation of analog-intensive IPs and help establish flows, methodologies, and processes for execution alongside peers.
  • Support the on-boarding and off-boarding of contingent layout staff and vendor partners as needed; help direct their day-to-day execution to ensure quality and schedule are met.
  • Work with other members of the team to deliver IPs, including project planning, schedule tracking, and report generation. Follow, augment, or put in place processes and methodologies for high-quality execution alongside peers.
  • Other
    • Embody our culture and values.

Qualifications
Required/minimum qualifications
  • Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
    • OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
    • OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
    • OR equivalent experience.

Other Requirements
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
    • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
    • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
  • Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation).
  • Ability to work in an "AI-first" environment using modern AI tools to accelerate discovery through hardware development.

Preferred Qualifications
  • 10+ years of experience in Analog Mask Layout execution and IP delivery, including delivery of medium-to-large complexity analog blocks into mass production.
  • 5+ years of lead experience covering day-to-day task coordination and overall delivery responsibilities across a layout team.
  • Proficient use of Electronic Design Automation (EDA) tools from Cadence, Mentor, and Synopsys, including advanced Schematic-Driven Layout (SDL).
  • Hands-on layout experience with high-performance analog blocks such as Voltage-Controlled Oscillators (VCOs), charge pumps, interpolators, bandgap references, Operational Transconductance Amplifiers (OTAs), Phase-Locked Loops (PLLs), Analog-to-Digital and Digital-to-Analog Converters (ADCs/DACs), Low-Dropout Regulators (LDOs), Serializer/Deserializers (SerDes), and other foundational analog blocks.
  • In-depth knowledge of analog design and layout guidelines for high-performance, high-speed, and/or low-power designs, including floor-planning, block-level routing, and large macro-level assemblies.
  • Knowledge of industry-standard analog layout techniques such as common-centroid layout, matching, symmetrical layouts, signal shielding, use of dummy devices, and thermal-aware layouts with consideration for Electromigration/IR-drop (EM/IR) and other analog-specific guidelines.
  • Demonstrated ability to coordinate execution with external vendors and contingent staff, including scoping deliverables, tracking progress, and accepting completed work.
  • Ability to learn cryogenic Process Design Kits (PDKs) and apply analog layout techniques to designs that operate at cryogenic temperatures.

#Quantum #QuantumCareers #MDQCareers
Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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About Microsoft

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Our infrastructure is comprised of a large global portfolio of more than 100 datacenters and 1 million servers. Our foundation is built upon and managed by a team of subject matter experts working to support services for more than 1 billion customers and 20 million businesses in over 90 countries worldwide. With environmental sustainability and optimization at the forefront of our datacenter design and operations, we continue to grow and evolve as we meet the ever-changing business demands that hold Microsoft as a world-class cloud provider.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Redmond, WA, US

Year founded

1975

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