1

Senior Analog Layout Engineer Jobs in Edison, NJ

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

Evaluating layout requirements for designs targeting different technologies (analog or digital ... engineering or related engineering degree, OR 4 years equivalent experience gained through work ...

Evaluating layout requirements for designs targeting different technologies (analog or digital ... engineering or related engineering degree, OR 4 years equivalent experience gained through work ...

Evaluating layout requirements for designs targeting different technologies (analog or digital ... engineering or related engineering degree, OR 4 years equivalent experience gained through work ...

The Senior PCB Layout Engineer contributes to the design and delivery of high-performance printed circuit boards that support scalable and manufacturable optical engine platforms. This role connects ...

Analog IC Design Engineer

Princeton, NJ · On-site

$81K - $108K/yr

Working with senior designers on designing, modeling and laying out analog/mixed circuit components ... Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops ...

Analog IC Design Engineer

Princeton, NJ · On-site

$81K - $108K/yr

Working with senior designers on designing, modeling and laying out analog/mixed circuit components ... Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops ...

Working with senior designers on designing, modeling and laying out analog/mixed circuit components ... Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops ...

Design and verification of analog circuits, including OpAmps, Comparators and Regulators * Support layout engineers with the layout of macro cells and ensure correct post-layout functionality * Work ...

IC Design Engineer IV

Princeton, NJ · On-site

$117K - $155K/yr

Design and verification of analog circuits, including OpAmps, Comparators and Regulators * Support layout engineers with the layout of macro cells and ensure correct post-layout functionality * Work ...

IC Design Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

Design and verification of analog circuits, including OpAmps, Comparators and Regulators * Support layout engineers with the layout of macro cells and ensure correct post-layout functionality * Work ...

IC Design Engineer IV

Princeton, NJ · On-site

$117K - $155K/yr

Design and verification of analog circuits, including OpAmps, Comparators and Regulators * Support layout engineers with the layout of macro cells and ensure correct post-layout functionality * Work ...

Design and verification of analog circuits, including OpAmps, Comparators and Regulators * Support layout engineers with the layout of macro cells and ensure correct post-layout functionality * Work ...

Design and verification of analog circuits, including OpAmps, Comparators and Regulators * Support layout engineers with the layout of macro cells and ensure correct post-layout functionality * Work ...

Senior Hardware Engineer

Matawan, NJ · On-site

$90 - $120/hr

Collaborate with optical, electrical, mechanical, and software engineers on integrated product ... PCB layout skills with emphasis on signal integrity, power integrity, and mixed-signal (analog ...

next page

Showing results 1-20

Senior Analog Layout Engineer information

See Edison, NJ salary details

$61.6K

$131K

$190K

How much do senior analog layout engineer jobs pay per year?

As of Aug 25, 2026, the average yearly pay for senior analog layout engineer in Edison, NJ is $131,018.00, according to ZipRecruiter salary data. Most workers in this role earn between $108,200.00 and $148,600.00 per year, depending on experience, location, and employer.

What is a senior analog layout engineer?

Senior Analog Layout Engineers are experienced professionals who design and implement the physical layout of analog integrated circuits (ICs) such as amplifiers, data converters, and power management chips. They translate circuit schematics into detailed layouts that ensure optimal electrical performance, reliability, and manufacturability. Their responsibilities include working closely with circuit designers, performing layout-versus-schematic (LVS) checks, and using specialized Electronic Design Automation (EDA) tools. Senior engineers often mentor junior staff and help resolve complex layout challenges. Their expertise is critical in ensuring the final chip meets specifications and industry standards.

What are the key skills and qualifications needed to thrive as a senior analog layout engineer?

To thrive as a Senior Analog Layout Engineer, you need deep knowledge of analog/mixed-signal IC layout, semiconductor device physics, and experience with advanced CMOS processes, typically supported by a relevant engineering degree. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and DRC/LVS verification systems is essential. Attention to detail, problem-solving, and strong collaboration skills set standout professionals apart in this role. These abilities ensure high-performance, reliable chip designs that meet stringent industry standards and project timelines.

What are some common challenges senior analog layout engineers face when collaborating with circuit designers, and how can they be addressed?

Senior Analog Layout Engineers often encounter challenges such as translating complex circuit schematics into efficient physical layouts while meeting stringent performance requirements. Miscommunications or differing priorities between layout engineers and circuit designers can lead to design iterations or delays. To address these challenges, it’s important to establish clear communication channels, participate in regular design reviews, and use collaborative tools for feedback and issue tracking. Being proactive in discussing layout constraints and providing early feedback can help ensure that both layout and performance goals are achieved efficiently.

What is the difference between Senior Analog Layout Engineer vs Analog IC Design Engineer?

AspectSenior Analog Layout EngineerAnalog IC Design Engineer
Primary FocusPhysical layout and implementation of analog circuitsDesign and simulation of analog circuits
Skills RequiredLayout tools, fabrication process knowledge, circuit understandingCircuit theory, schematic design, simulation skills
Work EnvironmentFoundries, semiconductor companies, R&D labsDesign teams, R&D departments, EDA tool usage
Common UsageInvolved in physical design phaseInvolved in circuit conceptualization and schematic design

While both roles require a strong understanding of analog circuits, the Senior Analog Layout Engineer focuses on translating circuit schematics into physical layouts, ensuring manufacturability and performance. In contrast, the Analog IC Design Engineer primarily designs and simulates the circuits themselves. Both roles often collaborate but differ in their core responsibilities and skill sets.

What cities near Edison, NJ are hiring for Senior Analog Layout Engineer jobs?

Cities near Edison, NJ with the most Senior Analog Layout Engineer job openings:

IC Layout Engineer III

Princeton, NJ • On-site

SRI International
Scientific Research and Development Services • 1 - 5K employees

$92K - $122K/yr

Full-time

Posted 14 days ago


Job description

Overview
SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC Layout and will be working closely with the SRI Princeton foundry and Design team in the development of form, fit and function emulation (not duplication) of obsolete microcircuits for the U.S. Government. Target microcircuits are emulated with pre-established gate arrays with only metallization determining the actual circuit function. The emulated design must meet all specifications and characteristics of the original microcircuit.
Responsibilities
  • Layout of IC designs for existing technologies (CMOS, BiCMOS, Bipolar etc)
  • Generating and/or supervising the creation of IC layout rules (LVS,DRC,ERC) for technologies in development
  • Evaluating layout requirements for designs targeting different technologies (analog or digital)
  • Documenting critical technology information to be used by Layout team
  • Evaluating and enhancing Place & Route algorithms and processes for complex digital designs
  • Contributing to layout tool suites by supporting and/or developing CAD scripts (Memory cell placement, antenna effect mitigation, etc)

Qualifications
  • BS in electrical engineering or related engineering degree, OR 4 years equivalent experience gained through work projects related to design and drafting without a degree.
  • 5 + years of relevant IC layout work experience.
  • Fundamental knowledge of Integrated Circuit CAD design.
  • Demonstrated analytical and systematic teamwork approach to troubleshooting.
  • Demonstrated ability to effectively communicate with team members (verbal and written).
  • Due to Government requirements candidates must be a US Citizen or Permanent Resident.

The salary range is: $92,160-$122,112. Salary ranges will vary and are based on several factors, including geographic location, market competitiveness and equity amongst internal employees in similar roles. Positions may also qualify for SRI's Pay for Outstanding Performance program or the annual Performance Based Compensation program. SRI also has a competitive benefits package, to view details please go to https://www.sri.com/resources/benefits/. SRI will accept applications until the position is filled.
SRI is an independent nonprofit research institute headquartered in Menlo Park, Calif., with a rich history of supporting government and industry. We create and deliver world-changing solutions for a safer, healthier, and more sustainable future. For almost 80 years, we have collaborated across technical and scientific disciplines to discover and develop groundbreaking products and technologies and bring innovations and ideas to the marketplace.