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Semiconductors Verification Manager Jobs (NOW HIRING)

Qorvo, Inc.

Senior Project Manager

Richardson, TX · On-site

... RF Semiconductors, RF Modules and Semiconductor wafer services for both Defense and Aerospace ... Qorvo is an E-Verify Employer. For more information, please see the Right to Work and E-Verify ...

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Semiconductors Verification Manager information

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How much do semiconductors verification manager jobs pay per year?

As of Sep 10, 2026, the average yearly pay for semiconductors verification manager in the United States is $95,625.00, according to ZipRecruiter salary data. Most workers in this role earn between $56,000.00 and $122,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Semiconductors Verification Manager job openings in the United States as of July 2026, with employment types broken down into 86% Full Time, 13% Part Time, and 1% Contract. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $95,625 per year, or $46 per hour.

Principal Digital IP Verification Engineer

Austin, TX

NXP Semiconductors
See more jobs at NXP Semiconductorsexternal

$134K - $164K/yr

Full-time

Re-posted 2 days ago

Job description

About the Role

This position is within the MME MCU/MPU Digital IP team. We develop best-in-class digital IPs for NXP's automotive and advanced microcontroller businesses, delivering sensor and processing technologies that enable secure, connected vehicles today and autonomous vehicles of the future.

Job Summary

  • Define and execute verification plans

  • Develop and implement verification testbenches

  • Develop testbench components such as drivers, monitors, and scoreboards, and leverage advanced UVM VIPs

  • Develop directed and constrained-random stimulus

  • Analyze RTL, functional coverage, and assertion coverage results

  • Define and develop functional coverage models

  • Develop and maintain SystemVerilog assertions (SVA)

  • Apply formal verification methodologies

  • Demonstrate strong debugging skills, including failure reproduction and root-cause analysis

  • Exhibit strong analytical and problem-solving skills; familiarity with major simulation and debug tools is a plus

Key Responsibilities

  • Drive a "zero-defect" mindset across the verification team

  • Provide technical leadership and guidance on complex verification challenges

  • Mentor and grow a small team of engineers

Cross-Functional Collaboration

  • Partner with local and global SoC and IP teams to drive best practices and continuous productivity improvements

  • Demonstrate outstanding problem-solving and analytical capabilities

Qualifications

  • BSEE with 8+ years of semiconductor industry experience, or

  • MSEE with 5+ years of experience, or

  • PhD with 3+ years of experience

Technical Skills

  • Knowledge of protocols such as DDR, PCIe, AMBA (CHI, ACE, AXI)

  • Strong expertise in Verilog, SystemVerilog (VHDL is a plus)

  • Experience with OVM/UVM and class-based verification methodologies

  • Experience with formal verification methodologies

  • Experience leveraging AI/LLM-based approaches to improve engineering efficiency

  • Test pattern debugging and validation on simulation and automated test environments

  • Low-power verification using CPF/UPF

  • Scripting in Python, Perl, and UNIX/Linux

  • Experience with FPGA/emulation/prototyping platforms (e.g., HAPS, Palladium, Zebu) is a plus

  • Understanding of power management concepts

  • Familiarity with functional and code coverage methodologies

Location

Austin, TX (Hybrid)

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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