Semiconductor Reliability Engineer Jobs in Maryland

This position is part of the National Institute of Standards (NIST) Professional Research Experience (PREP) program. NIST recognizes that its research staff may wish to collaborate with researchers at academic institutions on specific projects of mutual interest and thus requires that such institutions be the recipient of a PREP award. The PREP program requires staff from a wide range of backgrounds to work on scientific research in many areas. Employees in this position will perform technical work that underpins the scientific research of the collaboration.

Research Title:

Reliability testing of wide bandgap semiconductor power devices

U.S. Citizen Preferred

The work will entail:

Reliability is the most critical factor in power electronics. As systems face increasing electrical, thermal, and mechanical stress, individual components degrade, causing untimely failures. Rapid electrification and the aging grid infrastructure can only be addressed if the underlying power electronic components are reliable. Current testing standards for existing silicon-based electronics fail to accurately capture the performance and failure mechanisms of newer wide bandgap (WBG) semiconductor materials like SiC and GaN. Advantages of WBGs- such as higher efficiency, small footprint, higher power- can be overshadowed by reliability issues that standard silicon-based test methods cannot detect. Without accurate test protocols to evaluate reliability of emerging WBG semiconductors, manufacturers will face higher costs and will adopt them at lower rates. This project will aim to adopt a three-pillar measurement approach that can overcome the limitations of the current test protocols. This work will address electrical, material and mechanical degradation via real-time characterization methods. Pillar one is focused on building a dynamic testing apparatus for stress-testing of power devices under high voltage swings to capture the transient behaviors of internal resistance and threshold voltage hysteresis that occur in devices only when actively switching in a circuit. The second pillar will address dielectric breakdown at interfaces using AC gate stress testing under realistic loads. Finally, pillar three will employ an advanced Power Cycling Test (PCT) with microsecond resolution internal temperature measurements in order to correlate electrical load stressors with thermal stress and mechanical packaging failures. Our focus will be on active load' simulations rather than passive testing, therefore giving us and the industry high-quality data that is highly desired.

Key responsibilities will include but are not limited to:

- Build and fully characterize one or more dynamic testing circuits for stress-testing of power devices, such GaN HEMTs, under voltage or current transients.

- Evaluate dielectric breakdown at interfaces using AC gate stress testing under realistic loads

- Perform advanced power cycling measurements to evaluate thermal stress and packaging failures.

- Present results at internal and external meetings and conferences

- Write peer-reviewed journal articles on novel and important research findings

* A masters or a Ph. D. degree in Electrical or Mechanical Engineering, or a related field.

* 3 years of relevant experience, including graduate research work.

* Proficient in PCB layout and circuit simulations and modeling.

* Familiarity with data analysis techniques and mathematical computations using programming tools such as Python or MATLAB.

* A strong desire to collaborate with other researchers and be involved on various related projects.

* Strong oral and written communication skills.

Please upload the following with your application:

- CV/Resume

*Please limit C.V to 3 pages only and ONLY include a valid email address for your contact info. Your resume will not be considered if the following information is included on your CV/resume.

- Self portraits

- Phone number

- Home address/Country

- Citizenship status

- Languages spoken

- Sex/Gender

- Personal Interest

Privacy Act Statement

Authority: 15 U.S.C. * 278g-1(e)(1) and (e)(3) and 15 U.S.C. * 272(b) and (c)

Purpose: The National Institute for Standards and Technology (NIST) hosts the Professional Research Experience Program (PREP), which is designed to provide valuable laboratory experience and financial assistance to undergraduates, post-bachelor's degree holders, graduate students, master's degree holders, postdocs, and faculty.

PREP is a 5-year cooperative agreement between NIST laboratories and participating PREP Universities to establish a collaborative research relationship between NIST and U.S. institutions of higher education in the following disciplines, including (but not limited to) biochemistry, biological sciences, chemistry, computer science, engineering, electronics, materials science, mathematics, nanoscale science, neutron science, physical science, physics, and statistics. This collection of information is needed to facilitate the administrative functions of the PREP Program.

Salary Range

The referenced salary range represents the minimum and maximum salaries for this position and is based on Johns Hopkins University's good faith belief at the time of posting. Not all candidates will be eligible for the upper end of the salary range. The actual compensation offered to the selected candidate may vary and will ultimately depend on multiple factors, which may include the successful candidate's geographic location, skills, work experience, internal equity, market conditions, education/training and other factors, as reasonably determined by the University.

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