1

Sdc Designs Jobs in Texas (NOW HIRING)

Senior STA Engineer

Austin, TX · On-site

$152.40 - $217.20/hr

... CPU designs (≥ 2 GHz) * Expert‑level understanding of multi‑scenario STA, SDC constraints, and timing exceptions * Deep knowledge of OCV/AOCV/POCV margining and silicon correlation

Senior Structural Engineer

Houston, TX · On-site

$96K - $130K/yr

Experience with data center or mission-critical facility design (Risk Category IV) * Track record designing for high-seismic regions (SDC D, E, F) * Startup or high-growth company experience

RTL Engineer

Austin, TX · On-site

$250K - $375K/yr

Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff ... Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL * 5+ years designing ...

Lead RTL Engineer

Austin, TX · On-site

$101K - $133K/yr

Define and maintain SDC timing constraints. * Review all RTL code submissions for correctness ... Strong experience in Processor, DSP, or datapath-intensive designs. * Familiarity with advanced ...

You will closely interact with RTL designer to understand design intent and clock structure, with ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...

... designed to increase appointments, customer retention, and overall revenue growth. The ideal ... Experience in marketing, call center operations, BDC/SDC, customer retention, or AI-related roles ...

You will closely interact with RTL designer to understand design intent and clock structure, with ... SDC constraints generation and management, proficient in scripting languages (Tcl and Perl ...

You will closely interact with RTL designer to understand design intent and clock structure, with ... SDC constraints generation and management, proficient in scripting languages (Tcl and Perl ...

You will closely interact with RTL designer to understand design intent and clock structure, with ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...

... designed to increase appointments, customer retention, and overall revenue growth. The ideal ... Experience in marketing, call center operations, BDC/SDC, customer retention, or AI-related roles ...

... designed to increase appointments, customer retention, and overall revenue growth. The ideal ... Experience in marketing, call center operations, BDC/SDC, customer retention, or AI-related roles ...

next page

Showing results 1-20

Sdc Designs information

What is the difference between Sdc Designs vs Interior Designer?

AspectSdc DesignsInterior Designer
CredentialsTypically requires certification or training in design software and industry standardsOften holds a degree in interior design or related certification
Work EnvironmentDesign firms, architectural offices, or freelance projectsDesign studios, architectural firms, or independent consulting
Industry UsageUsed in architectural and construction projects for detailed design workUsed broadly for residential, commercial, and hospitality interior projects

While both Sdc Designs and Interior Designers work on creating functional and aesthetic spaces, Sdc Designs often focuses on technical design aspects, including detailed plans and specifications, whereas Interior Designers emphasize the overall aesthetic and space planning. Understanding these differences helps clients choose the right professional for their project needs.

Infographic showing various Sdc Designs job openings in Texas as of August 2026, with employment types broken down into 92% Full Time, 5% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution.

Physical Design Engineer (STA, SDC, MMMC) | San Diego, CA /Santa Clara, CA / Austin, TX | Onsite | L

Central Business Solutions

Austin, TX • On-site

$134K - $138K/yr

Full-time

Posted 13 days ago


Job description

Title: Static Timing Analysis (STA) / Timing Closure & Signoff Engineer
Function: Physical Design - Timing Signoff
Experience: 3 - 8 years of relevant STA / physical design experience
Engagement: Engineering services for a leading global SoC (System-on-Chip) manufacturer
Location: San Diego, CA /Santa Clara, CA / Austin, TX (or client site as applicable)
Education: B.E. / B.Tech. / M.E. / M.Tech. in ECE / EEE / VLSI / Microelectronics or equivalent

About the Role
We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon-ready timing signoff.
The ideal candidate has strong fundamentals in static timing analysis, hands-on experience with industry signoff tools, and a proven track record of closing timing on complex, high-frequency designs at advanced FinFET technology nodes.
Key Responsibilities
Timing constraints (SDC): Develop, review, validate, and maintain timing constraints - clock definitions, generated clocks, I/O delays, false paths, multicycle paths, and clock-domain-crossing (CDC) exceptions - and ensure constraint consistency and quality.
Timing signoff: Perform block-level and full-chip static timing analysis and signoff using Synopsys PrimeTime / PrimeTime SI (and/or Cadence Tempus) across a full multi-mode multi-corner (MMMC) setup.
Timing closure: Analyze and close setup, hold, recovery/removal, and transition/capacitance violations; generate and implement timing ECOs and coordinate fixes with the place-and-route team.
Signal integrity: Run crosstalk delay and noise (SI) analysis, identify and resolve SI-induced violations, and correlate with extraction and physical data.
Parasitic correlation: Set up and validate RC parasitic extraction and SPEF (StarRC / Quantus QRC), manage RC corners, and ensure extraction-vs-signoff correlation.
Variation-aware analysis: Apply OCV / AOCV / POCV (SOCV) derating methodologies and drive accurate margin-aware signoff.
Hierarchical timing: Build and validate timing abstracts / interface models (ETM / ILM), perform interface timing budgeting, and support top-level integration for hierarchical designs.
Low-power timing: Handle UPF-based multi-voltage / multi-power-domain designs, including level shifters, isolation cells, and power-aware timing checks.
Flow & automation: Automate and enhance timing analysis and ECO flows using TCL / Python / Perl; improve turnaround time and reporting.
Collaboration & signoff quality: Work with synthesis, P&R, CTS, DFT, and IR/EM teams; document methodology, present timing reviews, and provide silicon-ready signoff sign-off criteria and reports.
Required Skills & Experience (Must-Have)
Strong fundamentals in static timing analysis - setup/hold, recovery/removal, timing arcs, slack, path groups, clock latency, uncertainty, and derating concepts.
Hands-on experience with Synopsys PrimeTime / PrimeTime SI for block and/or full-chip timing signoff.
Proficiency in SDC constraint development, debug, and validation (clocks, I/O timing, exceptions, CDC).
Experience with MMMC (multi-mode multi-corner) analysis and closure.
Understanding of OCV / AOCV / POCV variation-aware timing methodologies.
Working knowledge of crosstalk / signal-integrity analysis and noise closure.
Familiarity with parasitic extraction and SPEF (StarRC / Quantus QRC) and RC corner concepts.
Solid understanding of the physical design flow - synthesis, place-and-route, and clock tree synthesis - and its interaction with timing.
Exposure to advanced technology nodes (16nm / 7nm / 5nm / 3nm FinFET).
Strong scripting skills in TCL (mandatory); Python or Perl for flow automation.
Good debugging skills, clear communication, and the ability to work in a cross-functional, delivery-driven team.