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Safety Validation Verification Engineer Jobs (NOW HIRING)

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141K/yr

We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies. As a UVM ...

ChipAgents

Formal Verification Engineer

San Jose, CA · On-site

$250/hr

You will play a central role in teaching our AI agents how verification engineers develop properties, analyze counterexamples, close proof convergence gaps, and validate RTL designs with mathematical ...

SIGNin Solutions Inc.

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Etched Design Verification Engineer 6 Openings Location: San Jose, CA & Austin, TX - onsite Please ... Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs ...

New

Intel Corporation

$105K - $200K/yr

Role and Impact As a CPU Design Verification Engineer, you'll play a pivotal role in ensuring the ... Develop and execute sophisticated verification plans to validate CPU logic against architectural ...

Talent2Win

Software Verification Engineer

Peru, IL · On-site

About the Role We're looking for an experienced Software Verification Engineer to help develop and validate software for safety-critical embedded systems used in aviation and automotive applications.

Intel Corporation

CPU Verification Engineer

Austin, TX · On-site

$134K/yr

Develop and execute sophisticated verification plans to validate CPU logic against architectural ... Partner closely with CPU architects, RTL developers, and physical design teams to verify complex ...

Anodize

Lead SoC Verification Engineer

Los Altos, CA · On-site

$161K/yr

As our Lead SoC Verification Engineer, you will help establish the verification and validation methodology for our end product. Responsibilities * Cross Functional reviews: Participate in ...

Broadcom Inc.

Verification Engineer

San Jose, CA · On-site

$120K - $192K/yr

Develop and execute verification plans for IP blocks at both block and system levels. * Build and ... Develop Python‑based behavioral models and validate designs against RTL implementations.

Nvidia

GPU Verification Engineer

Westford, MA

$141K/yr

We are now looking for a GPU Verification Engineer. NVIDIA is seeking best-in-class ASIC ... Design and develop test generators that will verify and validate the CPU and GPU interactions ...

Saigepartners

AMD/DMS Verification Engineer

San Jose, CA · On-site

$159K/yr

Build comprehensive mixed-signal verification environments to validate analog, digital, and mixed-signal functionality. * Collaborate with RF and analog design engineers to develop, integrate, and ...

Broadcom

Verification Engineer

Fort Collins, CO

$134K/yr

Develop and execute verification plans for IP blocks at both block and system levels * Build and ... Develop Python-based behavioral models and validate designs by comparing them against RTL ...

Broadcom, Inc.

Verification Engineer

San Jose, CA · On-site

$159K/yr

Develop and execute verification plans for IP blocks at both block and system levels * Build and ... Develop Python-based behavioral models and validate designs by comparing them against RTL ...

Anodize

Lead SoC Verification Engineer

Los Altos, CA

$161K/yr

As our Lead SoC Verification Engineer, you will help establish the verification and validation methodology for our end product. Responsibilities * Cross Functional reviews: Participate in ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract ... Develop directed and random verification tests to validate block and IP functionality * Develop ...

Nvidia

GPU Verification Engineer

Westford, MA · On-site

$141K/yr

We are now looking for a GPU Verification Engineer. NVIDIA is seeking best-in-class ASIC ... Design and develop test generators that will verify and validate the CPU and GPU interactions ...

Broadcom

Verification Engineer

San Jose, CA

$159K/yr

Develop and execute verification plans for IP blocks at both block and system levels * Build and ... Develop Python-based behavioral models and validate designs by comparing them against RTL ...

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How much do safety validation verification engineer jobs pay per hour?

As of Sep 10, 2026, the average hourly pay for safety validation verification engineer in the United States is $52.00, according to ZipRecruiter salary data. Most workers in this role earn between $39.42 and $63.22 per hour, depending on experience, location, and employer.

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Infographic showing various Safety Validation Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 78% Full Time, 18% Part Time, 2% Contract, and 1% Nights. Highlights an 99% Physical, and 1% Remote job distribution, with an average salary of $108,152 per year, or $52 per hour.

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ • On-site

Airspan
See more jobs at Airspanexternal

$141K/yr

Full-time

Re-posted 2 days ago

Job description

Airspan Careers
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Location: Warren, New Jersey, Plano, TX or REMOTE U.S.
Company: AirSpan Networks
About AirSpan
AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies.
Job Description
As a UVM Verification Engineer, you will be responsible for developing and executing test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of AirSpan's ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards.
Key Responsibilities
  • Develop and implement UVM-based verification plans and test strategies for FPGA designs.
  • Perform functional, system-level, and regression testing for digital hardware components.
  • Create test benches, test cases, and automation frameworks in System Verilog.
  • Analyze test results, debug issues, and collaborate with design teams to resolve defects.
  • Ensure compliance with industry standards and customer requirements.
  • Provide documentation and reports on test procedures, results, and defect tracking.
  • Continuously optimize test processes and tools to improve efficiency and accuracy.

Qualifications & Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
  • 10 years of experience in UVM-based verification of FPGA systems.
  • Strong understanding of SystemVerilog and Universal Verification Methodology (UVM).
  • Proficiency in scripting languages such as Python or Perl for automation.
  • Experience with simulation tools such as ModelSim or QuestaSim.
  • Experience with C/C++
  • Experience in implementing Bit Accurate Models and debugging DSP designs
  • Familiarity with debugging tools, coverage metrics, and formal verification techniques.
  • Strong problem-solving and analytical skills with attention to detail.
  • Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
  • Ability to work collaboratively in a fast-paced, cross-functional team environment.
  • Design experience a plus.

Preferred Skills
  • Experience in verification of communication protocols.
  • Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.
  • Understanding of hardware/software co-verification techniques.

Apply