F amiliarity with chip digital design flow, including RTL integration, simulation, STA. * U ... P hD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS * 8 + years of ...
F amiliarity with chip digital design flow, including RTL integration, simulation, STA. * U ... P hD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS * 8 + years of ...
Timing Radio Integration Engineer
Irvine, CA ยท On-site
$111K - $150K/yr
All of which is driven by an outstanding vertically coordinated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Timing Radio Integration Engineer
Irvine, CA ยท On-site
$111K - $150K/yr
All of which is driven by an outstanding vertically coordinated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Lead Frontend Integration Engineer
Santa Clara, CA ยท Hybrid
$122K - $165K/yr
Integrate AMD internal IPs RTL/DV environments into SoC * Debug function/performance of Graphics ... Bachelor or Masters Degree in Electrical Engineering, Computer Engineering or Computer Science This ...
Lead Frontend Integration Engineer
Santa Clara, CA ยท Hybrid
$122K - $165K/yr
Integrate AMD internal IPs RTL/DV environments into SoC * Debug function/performance of Graphics ... Bachelor or Masters Degree in Electrical Engineering, Computer Engineering or Computer Science This ...
... on RTL integration, timing constraints, and synthesis of designs.- Knowledge of FE flows like Lint & LEQ and scripting is a plusWork closely with other engineers that are members of the SOC Design ...
... on RTL integration, timing constraints, and synthesis of designs.- Knowledge of FE flows like Lint & LEQ and scripting is a plusWork closely with other engineers that are members of the SOC Design ...
CPU Design Architect / Principal Digital Design Engineer
Sunnyvale, CA ยท On-site
$237K/yr
Familiarity with chip digital design flow, including RTL integration, simulation, STA ... PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS * 8+ years of CPU ...
CPU Design Architect / Principal Digital Design Engineer
Sunnyvale, CA ยท On-site
$237K/yr
Familiarity with chip digital design flow, including RTL integration, simulation, STA ... PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS * 8+ years of CPU ...
Lead RTL/FPGA Design Engineer
$170K - $195K/yr
As the Lead RTL/FPGA Design Engineer on our Aalyria Space team, you will own the end to end the ... Oversee the integration of Forward Error Correction (FEC) engines and high-speed interfaces into ...
Lead RTL/FPGA Design Engineer
$170K - $195K/yr
As the Lead RTL/FPGA Design Engineer on our Aalyria Space team, you will own the end to end the ... Oversee the integration of Forward Error Correction (FEC) engines and high-speed interfaces into ...
Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ... Integration and Testing: Collaborate with hardware and software teams to integrate digital designs ...
Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ... Integration and Testing: Collaborate with hardware and software teams to integrate digital designs ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Integration and Testing: Collaborate with hardware and software teams to integrate digital designs ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Integration and Testing: Collaborate with hardware and software teams to integrate digital designs ...
Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ... Integration and Testing: Collaborate with hardware and software teams to integrate digital designs ...
Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ... Integration and Testing: Collaborate with hardware and software teams to integrate digital designs ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Integration and Testing: Collaborate with hardware and software teams to integrate digital designs ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Integration and Testing: Collaborate with hardware and software teams to integrate digital designs ...
SoC Design/Integration & Synthesis Engineer
$181K - $318K/yr
... RTL integration, timing constraints, and synthesis of designs. - Knowledge of FE flows like Lint & LEQ and scripting is a plus Work closely with other engineers that are members of the SOC Design ...
SoC Design/Integration & Synthesis Engineer
$181K - $318K/yr
... RTL integration, timing constraints, and synthesis of designs. - Knowledge of FE flows like Lint & LEQ and scripting is a plus Work closely with other engineers that are members of the SOC Design ...
Front-End ASIC Design Engineer - [FullTime] (IK)
Milpitas, CA ยท On-site
$175K - $200K/yr
RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring-up. Ensure deadlines ...
Front-End ASIC Design Engineer - [FullTime] (IK)
Milpitas, CA ยท On-site
$175K - $200K/yr
RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring-up. Ensure deadlines ...
Timing Radio Integration Engineer
$171K - $302K/yr
Description As a Timing Integration Engineer, you will be a key member of the radio team ... Solid digital background in RTL design, synthesis and FE-STA to be able to work with digital teams ...
Timing Radio Integration Engineer
$171K - $302K/yr
Description As a Timing Integration Engineer, you will be a key member of the radio team ... Solid digital background in RTL design, synthesis and FE-STA to be able to work with digital teams ...
Timing Radio Integration Engineer
$171K - $302K/yr
Description As a Timing Integration Engineer, you will be a key member of the radio team ... Solid digital background in RTL design, synthesis and FE-STA to be able to work with digital teams ...
Timing Radio Integration Engineer
$171K - $302K/yr
Description As a Timing Integration Engineer, you will be a key member of the radio team ... Solid digital background in RTL design, synthesis and FE-STA to be able to work with digital teams ...
Timing Radio Integration Engineer
$171K - $302K/yr
Description As a Timing Integration Engineer, you will be a key member of the radio team ... Solid digital background in RTL design, synthesis and FE-STA to be able to work with digital teams ...
Timing Radio Integration Engineer
$171K - $302K/yr
Description As a Timing Integration Engineer, you will be a key member of the radio team ... Solid digital background in RTL design, synthesis and FE-STA to be able to work with digital teams ...
Radio Integration Engineer
$171K - $302K/yr
Description As a Radio Integration Engineer, you will be responsible for architecting, implementing ... Collaborating with the SOC team, PHY, RTL, and PD teams on the analog-to-digital interface ...
Radio Integration Engineer
$171K - $302K/yr
Description As a Radio Integration Engineer, you will be responsible for architecting, implementing ... Collaborating with the SOC team, PHY, RTL, and PD teams on the analog-to-digital interface ...
Radio Integration Engineer
$171K - $302K/yr
Description As a Radio Integration Engineer, you will be responsible for architecting, implementing ... Collaborating with the SOC team, PHY, RTL, and PD teams on the analog-to-digital interface ...
Radio Integration Engineer
$171K - $302K/yr
Description As a Radio Integration Engineer, you will be responsible for architecting, implementing ... Collaborating with the SOC team, PHY, RTL, and PD teams on the analog-to-digital interface ...
This role drives RTL integration through synthesis, timing analysis, and tapeout readiness ... engineering teams and external backend partners to deliver successful first-pass silicon. Key ...
Quick apply
This role drives RTL integration through synthesis, timing analysis, and tapeout readiness ... engineering teams and external backend partners to deliver successful first-pass silicon. Key ...
Radio Integration Engineer
$171K - $302K/yr
Description As a Radio Integration Engineer, you will be responsible for architecting, implementing ... Collaborating with the SOC team, PHY, RTL, and PD teams on the analog-to-digital interface ...
Radio Integration Engineer
$171K - $302K/yr
Description As a Radio Integration Engineer, you will be responsible for architecting, implementing ... Collaborating with the SOC team, PHY, RTL, and PD teams on the analog-to-digital interface ...
Front-End ASIC Design Engineer - [FullTime] (IK)
Milpitas, CA ยท On-site
$175K - $200K/yr
RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring-up. ยท Ensure ...
Quick apply
Front-End ASIC Design Engineer - [FullTime] (IK)
Milpitas, CA ยท On-site
$175K - $200K/yr
RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring-up. ยท Ensure ...
Rtl Integration Engineer information
See salary details
$44.5K - $56.2K
0% of jobs
$56.2K - $68K
2% of jobs
$68K - $79.7K
3% of jobs
$79.7K - $91.4K
7% of jobs
$91.4K - $103.1K
10% of jobs
$104.7K is the 25th percentile. Wages below this are outliers.
$103.1K - $114.9K
16% of jobs
The median wage is $121.3K / yr.
$114.9K - $126.6K
21% of jobs
$136.9K is the 75th percentile. Wages above this are outliers.
$126.6K - $138.3K
18% of jobs
$138.3K - $150K
10% of jobs
$150K - $161.8K
7% of jobs
$161.8K - $173.5K
5% of jobs
$44.5K
$124.3K
$173.5K
How much do rtl integration engineer jobs pay per year?
As of Jun 8, 2026, the average yearly pay for rtl integration engineer in the United States is $124,275.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,000.00 and $140,000.00 per year, depending on experience, location, and employer.
What is the difference between Rtl Integration Engineer vs Rtl Firmware Engineer?
| Aspect | Rtl Integration Engineer | Rtl Firmware Engineer |
|---|---|---|
| Primary Focus | Integrating RTL components into larger systems and ensuring compatibility | Developing and optimizing RTL code for hardware design |
| Required Skills | RTL integration, verification, scripting, hardware understanding | RTL coding, hardware description languages, simulation |
| Work Environment | System integration teams, hardware design labs | Hardware design teams, FPGA/ASIC development |
| Common Certifications | ASIC/FPGA design, verification tools | VHDL/Verilog certifications, FPGA design courses |
While both roles involve RTL, the Rtl Integration Engineer focuses on integrating RTL components into larger systems, ensuring compatibility and system functionality. The Rtl Firmware Engineer primarily develops and optimizes RTL code for hardware design. They often work closely but have distinct responsibilities within hardware development projects.
$237K/yr
Other
Posted 26 days ago
Job description
Job Description:
Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in:ย
Minimum Qualifications:ย
Preferred Qualifications:ย
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