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Rtl Design Jobs in Texas (NOW HIRING)

SambaNova

Principal RTL Design Engineer

Austin, TX

About the team The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out ...

SambaNova

Principal RTL Design Engineer

Austin, TX · On-site

$180K - $255K/yr

About the team The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out ...

IC Enable

RTL Design/AMS Verification Engineer

Richardson, TX · On-site +1

$122K - $149K/yr

We are seeking an experienced RTL Design / AMS Verification Engineer to support digital and mixed-signal IC development from architecture through implementation and verification. The ideal candidate ...

Tenstorrent

Sr. Engineer, CPU RTL Design

Austin, TX · On-site

$100K - $500K/yr

We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You'll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and ...

Intel Corporation

CPU RTL Design Engineer

Austin, TX · On-site

$141K - $269K/yr

Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU. * Participate in defining the architecture and microarchitecture features of the CPU design.

Intel

CPU RTL Design Engineer

Austin, TX

$141K - $269K/yr

Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU. * Participate in defining the architecture and microarchitecture features of the CPU design.

Intel

Senior CPU RTL Design Engineer

Austin, TX · On-site

As a Senior CPU RTL Design Engineer, you will define, develop, and optimize key microarchitectural features that power Intel's next-generation processors. In this role, you will contribute to CPU ...

Quest Global

RTL Design and Architect lead

Austin, TX · On-site

Work with Design Verification team and Physical Design team to take the product from RTL to GDSII. Prior experience on control loops, micro-controller integration, high speed peripherals, chiplet ...

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$129.8K

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How much do rtl design jobs pay per year?

As of Sep 3, 2026, the average yearly pay for rtl design in Texas is $129,843.00, according to ZipRecruiter salary data. Most workers in this role earn between $126,700.00 and $126,700.00 per year, depending on experience, location, and employer.

What is an RTL design?

An RTL (Register Transfer Level) Design job involves designing and implementing digital circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL engineers translate high-level specifications into synthesizable logic, ensuring functionality, power efficiency, and performance. They collaborate with verification engineers to test and debug designs before fabrication. This role is crucial in developing ASICs, FPGAs, and other digital hardware components.

What does an RTL design engineer do?

A typical day for an RTL Design engineer involves writing and optimizing RTL code, running simulations, debugging designs, and reviewing results from verification teams. Collaboration is key, as you will frequently interact with verification engineers, physical design teams, and architects to ensure the design meets both functional and performance requirements. You may also participate in design reviews, resolve issues found during testing, and work with project managers to meet deadlines. This cross-functional teamwork creates a dynamic environment where communication and problem-solving skills are highly valued, helping ensure the successful delivery of silicon products.

What are the key skills and qualifications needed for RTL design?

To thrive as an RTL Design engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages such as Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, and experience with FPGA/ASIC flows, are highly valuable, as are relevant industry certifications. Strong problem-solving skills, attention to detail, and effective communication foster successful collaboration with verification and physical design teams. These skills are crucial for delivering robust, efficient hardware solutions in complex chip development projects.

What are the most commonly searched types of Rtl Design jobs in Texas?

The most popular types of Rtl Design jobs in Texas are:

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For Rtl Design jobs in Texas, the most frequently searched job titles are:

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Rtl Design jobs near you
Infographic showing various Rtl Design job openings in Texas as of August 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $129,843 per year, or $62.4 per hour.

Principal RTL Design Engineer

SambaNova

Austin, TX

Full-time

Posted 15 days ago

Job description

About the team

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with physical design.

About the role

SambaNova is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for our next-generation Reconfigurable Dataflow Unit (RDU), the silicon behind our AI acceleration systems. This is a senior individual contributor role where you'll take a block from microarchitecture specification through RTL, quality closure, and tape-out, owning the power, performance, and area trade-offs along the way. Frequency targets are aggressive, so how you pipeline a datapath and where you spend area to buy timing are essential aspects of the role.

Responsibilities

Some of your responsibilities will include:

  • Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute, memory, or on-chip network subsystems
  • Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
  • Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
  • Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
  • Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
  • Work with architects and software teams to prototype and evaluate features that improve application-level performance
  • Drive AI, automation, and new EDA tool methodologies into the design flow
  • Set the technical bar in design reviews and mentor design engineers
Required Qualifications
  • B.S. in Electrical Engineering, Computer Engineering, or Computer Science
  • 7+ years of industry experience in ASIC RTL design
  • Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
  • High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets
  • Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures
  • Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
  • Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team
  • Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
  • Demonstrated technical leadership without formal authority, including setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers
  • Scripting in Python for design and flow automation
Preferred Qualifications
  • M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
  • Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
  • Industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
  • AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures
  • Formal property checking applied to design intent
  • Advanced TSMC nodes and multi-die or chiplet design
  • Performance modeling and analysis to support architectural trade-offs
  • Fluency with Claude or other AI tools applied to RTL design and flow development

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