Tenstorrent is looking for a Mixed-Signal IC Layout Design Engineer to own a fullcustom layout for highperformance analog and mixedsignal IP in advanced FinFET nodes. You'll translate schematics into manufacturable layouts that hit aggressive performance, power, area, and reliability targets, and integrate these blocks cleanly into larger SoCs.
This role is remote, based out of North America.
We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting
Who You Are
- An experienced analog/mixedsignal IC layout engineer with 5 years experience delivered silicon in CMOS/FinFET nodes. Deep proficiency in Cadence Virtuoso (XL/GXL) or equivalent custom layout environments, including constraintdriven layout and PCells.
- Strong understanding of CMOS devices, interconnect stacks, and advancednode rules, including multipatterning, density/fill, and lithographydriven constraints.
- Fluent in physical verification flows (Calibre, PVS, Assura, etc.) for DRC, LVS, ERC, LPE/RC, DFM, and antenna checks as well as being comfortable designing for matching, coupling/noise, IR/EM, ESD, and latchup in mixedsignal environments.
- Detailoriented and organized, able to own complex blocks independently while communicating effectively with distributed design teams.
- Bonus points if you bring experience in advanced FinFET nodes (7/5/3 nm), highspeed / RFadjacent circuits (SerDes, CDR, LNAs, VCOs, RF frontends), and scripting (SKILL, Python, Tcl/Perl) to automate layout and verification.
What We Need
- Partner closely with circuit designers to plan and implement fullcustom analog/mixedsignal layouts for blocks such as PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, and highspeed I/O. Build optimized floorplans and routing that balance area, parasitics, matching, and congestion for both blocklevel IP and toplevel SoC integration.
- Apply bestpractice layout techniques (commoncentroid / interdigitated devices, symmetric differential routing, guard rings, shielding, isolation, dummy devices, etc.) to meet stringent matching, noise, and accuracy specs. Optimize for parasitic R/C, coupling, IR drop, and electromigration to achieve noise, timing, and power targets.
- Run and debug DRC, LVS, ERC, DFM, and antenna checks with Synopsys ICV or Siemens Calibre, driving all violations to closure. Support postlayout extraction and simulation, iterating layout with circuit designers until full spec closure.
- Leverage Synopsys Custom Compiler and Cadence Virtuoso along with physical verification tool suites, ideally on TSMC and Samsung FinFET processes from 12 nm down to 2 nm.
- Where possible, develop and use layout methodology and automation (Python, Tcl, SKILL, etc.) to raise quality and productivity for the broader team.
What You'll Learn
- How to implement and integrate highspeed, highprecision analog/mixedsignal IP into complex SoCs in cuttingedge FinFET technologies.
- Advanced techniques for balancing PPA (performance, power, area) in mixedsignal layouts under tight matching, noise, and reliability constraints.
- Practical exposure to stateoftheart verification and DFM flows (R/C extraction, EM/IR, antenna, advanced fill) across leading foundry processes.
- How to scale your impact via methodology and automation, building scripts and flows that improve consistency, turnaround time, and silicon quality for the entire layout team.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.