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Remote Uvm Jobs (NOW HIRING)

Redolent, Inc.

US_West | Infrastructure Engineer_L3

$169K/yr

Redmond, WA Hybrid (Remote option allowed) Minimum Qualifications • Track record of 'first-pass ... UVM/SV (Priority: 1) Python/TCL/Perl (Priority: 3) Synopsys/Cadence EDA Design/Verification tools ...

Mercor

RTL Design Engineer - AI Tools

San Francisco, CA · Remote

$100 - $175/hr

Remote Duration: 3+ months Commitment: 40 hours/week Role Responsibilities * Evaluate digital chip ... Strong proficiency in Verilog/SystemVerilog and UVM . * Solid understanding of digital design ...

New

Eocene Environmental Group

$23 - $27/hr

... Remote Position. Must be a resident of California, and live within the Central Valley or Central Coast **Experience with Utility Vegetation Management (UVM) required, including proficiency in ArcGIS ...

University of Vermont Medical Center

Staff Accountant

$37.34 - $44.81/hr

Abby Luck This is a remote position. JOB SUMMARY: The System Staff Accountant is responsible for the following: * Provide support through training and assistance as well as guidance to all UVM Health ...

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Remote Uvm information

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How much do remote uvm jobs pay per hour?

As of Jun 5, 2026, the average hourly pay for remote uvm in the United States is $21.50, according to ZipRecruiter salary data. Most workers in this role earn between $18.03 and $22.84 per hour, depending on experience, location, and employer.

What is a Remote UVM job?

A Remote UVM job typically involves working from a remote location to develop, implement, and verify digital designs using the Universal Verification Methodology (UVM). UVM is a standardized methodology used in the semiconductor industry for verifying integrated circuit designs, particularly those written in SystemVerilog. Professionals in this role create testbenches, develop reusable verification components, and execute simulation-based verification processes to ensure chip designs function as intended. Remote UVM engineers collaborate with design and verification teams, often using online tools and communication platforms to coordinate their work.

What is the difference between Remote Uvm vs Remote Uvm?

AspectRemote UvmRemote Uvm
Required CredentialsUVM certification, FPGA/ASIC knowledgeUVM certification, FPGA/ASIC knowledge
Work EnvironmentRemote, collaborative design teamsRemote, collaborative design teams
Industry UsageHardware verification, semiconductor industryHardware verification, semiconductor industry
Common Search/ComparisonYesYes

The comparison between Remote Uvm and Remote Uvm shows they are essentially the same role, focusing on hardware verification using UVM methodology. Both require similar certifications, work in remote environments, and are used within the semiconductor industry. The key difference often lies in specific project focus or employer terminology, but generally, they are interchangeable in job searches and industry discussions.

What are the key skills and qualifications needed to thrive as a Remote UVM (Universal Verification Methodology) Engineer, and why are they important?

To thrive as a Remote UVM Engineer, you typically need a solid background in digital design verification, SystemVerilog, and a degree in electrical or computer engineering. Proficiency with simulation tools like Mentor Graphics Questa, Synopsys VCS, and advanced knowledge of UVM libraries is essential. Strong problem-solving abilities, attention to detail, and effective remote communication skills help professionals excel in distributed teams. These competencies ensure accurate verification of complex designs, efficient collaboration, and the successful delivery of high-quality hardware products.

How do Remote UVM engineers typically collaborate with distributed teams to ensure effective verification coverage?

Remote UVM engineers often utilize collaborative tools such as version control systems, video conferencing, and project management platforms to maintain clear communication with distributed teams. Regular sync meetings, code reviews, and shared documentation help ensure alignment on verification plans and progress. Effective collaboration is crucial for resolving design ambiguities, tracking bugs, and achieving comprehensive coverage in a remote environment. Proactively reaching out to designers, architects, and fellow verification engineers is key to overcoming challenges posed by physical distance.
Infographic showing various Remote Uvm job openings in the United States as of May 2026, with employment types broken down into 100% Part Time. Highlights an 94% Physical, 4% Hybrid, and 2% Remote job distribution, with an average salary of $44,724 per year, or $21.5 per hour.
US_West | Infrastructure Engineer_L3

US_West | Infrastructure Engineer_L3

Redolent, Inc.

Remote

$169K/yr

Contractor

Posted 18 days ago

Job description

Description:
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Job Description: SOC Design Verification Engineer
Location: Redmond, WA
Hybrid (Remote option allowed)
Minimum Qualifications
• Track record of 'first-pass success' in ASIC development cycles.
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8 to 10 years of hands-on experience in SystemVerilog/UVM methodology
• Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation.
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
Preferred Qualifications
• Experience verifying GPU/CPU designs.
• Experience in development of UVM based verification environments from scratch.
• Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.
• Experience with revision control systems like Mercurial(Hg), Git or SVN.
• Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet.
• Experience working across and building relationships with cross-functional design, model and emulation teams.
• Define and implement SoC verification plans, build verification test benches to enable sub-system/SoC level verification.
• Develop functional tests based on verification test plan.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
UVM/SV (Priority: 1)
Python/TCL/Perl (Priority: 3)
Synopsys/Cadence EDA Design/Verification tools (Priority: 1)
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details
  • Global Grade : C
  • Named Job Posting? (if Yes - needs to be approved by SCSC) : No
  • Remote work possibility : No
  • Global Role Family : 60239 (P) Cloud Infrastructure
  • Global Technical Skills Family : 6241 (T) Configuration Management & Versioning Tools
  • Local Role Name : SOC Design Verification Engineer
  • Local Skills : Julie Skidmore
  • Languages Required: : English
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About Redolent

Sourced by ZipRecruiter

Redolent, a dynamic and rapidly expanding company committed to excellence in software solutions, where success is fueled by a combination of technical expertise and efficient management practices. Our solutions create a measurable delta in our clients’ productivity and profitability, contributing to their growth and success.

Industry

It services

Company size

51 - 200 Employees

Headquarters location

San Jose, CA, US

Year founded

2008

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