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Remote Rtl Design Jobs in Palo Alto, CA (NOW HIRING)

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Remote Rtl Design information

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$94.6K

$163.8K

$214.5K

How much do remote rtl design jobs pay per year?

As of Sep 8, 2026, the average yearly pay for remote rtl design in Palo Alto, CA is $163,830.00, according to ZipRecruiter salary data. Most workers in this role earn between $159,900.00 and $159,900.00 per year, depending on experience, location, and employer.

What is a remote RTL design job?

Remote RTL (Register Transfer Level) Design jobs involve creating and verifying digital circuit designs using hardware description languages like Verilog or VHDL, while working from a remote location. RTL designers translate system requirements into functional hardware blocks, simulate their operation, and ensure they meet performance and power specifications. These roles are common in semiconductor and electronics companies, enabling professionals to collaborate with global teams without being onsite. Remote RTL designers typically use cloud-based tools and platforms to access design environments and communicate with colleagues. Strong knowledge of digital logic, hardware design languages, and industry-standard EDA tools is essential for these positions.

What are the key skills and qualifications needed to thrive as a remote RTL design engineer?

To thrive as a Remote RTL Design Engineer, you need a solid background in digital logic design, Verilog or VHDL programming, and a relevant engineering degree. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis are typically required. Strong problem-solving, attention to detail, and effective remote communication skills are essential for collaborating with distributed teams. These competencies ensure the creation of reliable, high-performance hardware designs and efficient teamwork in a remote environment.

What are some common challenges faced by remote RTL design engineers, and how can they be addressed?

Remote RTL Design engineers often encounter challenges such as effective communication with cross-functional teams, managing version control for hardware description files, and ensuring timely feedback on design iterations. To address these, many teams utilize collaborative tools like version control systems (e.g., Git), regular video meetings, and shared project management platforms. Establishing clear documentation and proactive communication habits can further minimize misunderstandings and keep projects on track, fostering a productive remote work environment.

What is the difference between Remote Rtl Design vs Remote Digital IC Design?

AspectRemote Rtl DesignRemote Digital IC Design
Required CredentialsBachelor's in Electrical Engineering or related; knowledge of HDL (VHDL/Verilog)Bachelor's in Electrical Engineering or related; knowledge of HDL and circuit design
Work EnvironmentDesigning RTL code, simulation, verification, often in a collaborative team settingDesigning digital integrated circuits, layout, verification, often in a team
Industry UsageSemiconductor, electronics companies, chip design firmsSemiconductor, electronics, and integrated circuit manufacturing

Remote Rtl Design focuses on creating and verifying RTL code for digital circuits, while Remote Digital IC Design involves designing entire integrated circuits. Both roles require similar technical skills and often overlap in the semiconductor industry, but they differ in scope and specific tasks.

What are the most commonly searched types of Rtl Design jobs in Palo Alto, CA?

The most popular types of Rtl Design jobs in Palo Alto, CA are:

What are popular job titles related to Remote Rtl Design jobs in Palo Alto, CA?

For Remote Rtl Design jobs in Palo Alto, CA, the most frequently searched job titles are:

What job categories do people searching Remote Rtl Design jobs in Palo Alto, CA look for?

The top searched job categories for Remote Rtl Design jobs in Palo Alto, CA are:

What cities near Palo Alto, CA are hiring for Remote Rtl Design jobs?

Cities near Palo Alto, CA with the most Remote Rtl Design job openings:

Remote Rtl Design jobs near you
Infographic showing various Remote Rtl Design job openings in Palo Alto, CA as of September 2026, with employment types broken down into 78% Full Time, and 22% Contract. Highlights an 100% Remote job distribution, with an average salary of $163,830 per year, or $78.8 per hour.

Principal Software Engineer, Security Solutions

Campbell, CA • On-site, Remote

Arteris
Semiconductor and Electronic Component Manufacturing • 11 - 50 employees
Learn more about Arterisexternal

$155K - $208K/yr

Full-time

Re-posted 16 days ago

Job description

Principal Engineer Security Solutions Engineering

Location: Campell, CA

 

Arteris connects innovation.
Our technology helps the world’s most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, specifically SoCs and chiplets. From the car you drive, to the AI in the cloud, Arteris connects the innovative tech that shapes tomorrow.

What You’ll Do as a Principal Engineer of Security Solutions Engineering at Arteris

Join our innovative team and help shape the future of semiconductor technology, specifically hardware security solutions. A Principal Engineer operates as a core member of the Research and Development team, establishing current and future architectures, implementing innovative solutions, and ensures that engineering commitments are credible, visible, and reliably delivered.  Reporting to the senior Director of engineering, this technical leader architects and builds innovative solutions, mentors junior engineers, clearly communicates technical strategy, translates complex concepts for non-technical stakeholders, ensures risks are identified early and aligns with the strategy of the product team. 

Key Responsibilities

  • Technical Strategy & Architecture
  • Define and own the long‑term technical strategy for core hardware security engines, balancing innovation, scalability, and product quality.
  • Review and challenge architectural and algorithmic decisions made by senior technical staff (architects, principal engineers) for high‑performance, memory‑efficient, and scalable analysis systems operating on very large designs.
  • Set technical standards for algorithmic rigor, performance benchmarking, regression testing, and release readiness.
  • Execution & Delivery
  • Contribute strategy and implementation of software products, including correctness, runtime performance, memory footprint, and scalability.
  • Ensure correctness, determinism, and debuggability of complex multi‑threaded and distributed systems.
  • Drive predictable execution from research through productization in a commercial EDA environment.
  • Organization & Talent
  • Foster a culture of technical excellence, peer review, and evidence‑based decision making.
  • Develop future technical leaders within a mixed research and development engineering organization.
  • Cross‑Functional Leadership
  • Communicate complex algorithmic issues clearly to non‑specialist stakeholders.

What You Bring

  • At least 8 years of experience architecting, developing and delivering complex C++ commercial technical applications.
  • Demonstrated history of technical leadership involving setting product direction and owning outcomes of complex algorithms (quality, runtime, reliability, user experience and memory consumption).
  • Hands-on depth in at least one major EDA area (e.g., simulation, synthesis, formal verification, equivalence checking, static analysis), with the ability to evaluate architectural tradeoffs and algorithms.
  • Strong grounding in algorithms and data structures for digital logic analysis and transformation.
  • Practical understanding of SoC design and verification flows and how EDA tools are used in production environments.
  • Track record building performant, scalable systems (runtime/memory, concurrency, distributed execution) that can operate on multi-billion gate designs.
  • Excellent communication skills with the ability to clearly articulate risks, tradeoffs, and outcomes to senior leadership and customers.
  • Understanding and experience with hardware description languages (Verilog, SystemVerilog, VHDL) and simulation semantics.
  • Expert programming and debug skills in modern C++.
  • Proficiency working in Linux.
  • Must exhibit a collaborative technical style and be able to work well with cross functional teams.
  • Ability to operate effectively in a fast-paced, high-accountability environment with competing priorities.
  • This position is based in Campbell CA, but highly qualified remote candidates located anywhere in the continental USA will be considered. Travel will be required for team and/or customer meetings.

Bonus Points If You Have

  • Relevant work experience is in the domains of Simulation, Synthesis or Formal Verification or similar products.
  • Familiarity with hardware security analysis or security-oriented verification tools
  • Understanding of RTL/gate-level simulation and debugging.
  • Experience in the implementation and verification of SoC designs.

Education Requirements

  • Bachelor’s degree in Computer Science or Electrical Engineering (MS/PhD preferred).

Estimated Base Salary

195,000 to 210,000 annually. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

About Arteris

Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster. Learn more at arteris.com.

With over 300 team members headquartered in Silicon Valley and offices around the world, we work with startups and global tech leaders alike to build the next generation of electronic products. We believe in people, purpose and impact. Join us and help shape what comes next.

ARTERIS logo

About ARTERIS

Sourced by ZipRecruiter

Industry

Semiconductor and electronic component manufacturing

Company size

11 - 50 Employees

Headquarters location

Campbell, CA, US

Year founded

2003

Social media

Twitter

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