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Remote Matlab Simulation Engineer Jobs in San Jose, CA

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the ... Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and ...

SimX, Inc

Territory Manager (Remote)

San Francisco, CA · Remote

$70K - $90K/yr

Our product is the first comprehensive professional-grade VR medical simulation system, and it is ... scientists, engineers, and many others, all of whom have dedicated their time to achieving our ...

Oklo

Human Factors Engineer

Santa Clara, CA · On-site +1

Define Human System Interface (HIS) requirements for control rooms, local control stations, remote ... mockups, simulator exercises, walkdowns, tabletop exercises, human-in-the-loop evaluations ...

Oklo

Human Factors Engineer

Santa Clara, CA · On-site +1

Define Human System Interface (HIS) requirements for control rooms, local control stations, remote ... mockups, simulator exercises, walkdowns, tabletop exercises, human-in-the-loop evaluations ...

General Motors

Principal AI/ML Engineer

Sunnyvale, CA · On-site +1

$296K - $423K/yr

Architect scalable training pipelinesusinglarge-scaledriving datasets and simulation environments ... Remote/Hybrid: Thisrole is based remotely but if you live within a 50-mile radius of Austin ...

AttoTude

MMIC Design Engineer

Menlo Park, CA · On-site +1

... design, simulation, verification, layout and evaluation * Drive high-speed IC design, >100GHz ... Master's Degree (MEng) in Electrical Engineering or related field is required * A Ph.D. in ...

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All JobsMatlab Simulation Engineer JobsRemote Matlab Simulation Engineer JobsRemote Matlab Simulation Engineer Jobs in San Jose, CA

Remote Matlab Simulation Engineer information

See San Jose, CA salary details

$45.7K

$144.6K

$223.3K

How much do remote matlab simulation engineer jobs pay per year?

As of Sep 7, 2026, the average yearly pay for remote matlab simulation engineer in San Jose, CA is $144,623.00, according to ZipRecruiter salary data. Most workers in this role earn between $107,800.00 and $171,700.00 per year, depending on experience, location, and employer.

What is the difference between Remote Matlab Simulation Engineer vs Remote Data Analyst?

AspectRemote Matlab Simulation EngineerRemote Data Analyst
Required SkillsMatlab, simulation, modeling, programmingData analysis, statistics, Excel, SQL
Work EnvironmentEngineering teams, simulation labs, R&DBusiness teams, data warehouses, reporting tools
Industry UsageEngineering, aerospace, automotive, researchFinance, marketing, healthcare, tech

The Remote Matlab Simulation Engineer primarily focuses on developing and running simulations using Matlab for engineering projects, while the Remote Data Analyst interprets data to support business decisions. Both roles require analytical skills but differ in technical tools and industry applications. Understanding these differences helps job seekers target the right roles based on their skills and career goals.

What are the most commonly searched types of Matlab Simulation Engineer jobs in San Jose, CA?

The most popular types of Matlab Simulation Engineer jobs in San Jose, CA are:

What are popular job titles related to Remote Matlab Simulation Engineer jobs in San Jose, CA?

For Remote Matlab Simulation Engineer jobs in San Jose, CA, the most frequently searched job titles are:

What job categories do people searching Remote Matlab Simulation Engineer jobs in San Jose, CA look for?

The top searched job categories for Remote Matlab Simulation Engineer jobs in San Jose, CA are:

What cities near San Jose, CA are hiring for Remote Matlab Simulation Engineer jobs?

Cities near San Jose, CA with the most Remote Matlab Simulation Engineer job openings:

Remote Matlab Simulation Engineer jobs near you
Infographic showing various Remote Matlab Simulation Engineer job openings in San Jose, CA as of August 2026, with employment types broken down into 91% Full Time, 5% Part Time, and 4% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $144,623 per year, or $69.5 per hour.

Lead ASIC DFT Engineer

Purple Hires Inc

San Jose, CA • Remote

Contractor

Re-posted 22 days ago

Job description

Title - Lead ASIC DFT Engineer

Location – Remote (must be aligned with PST time zone)

 
Below is the detailed job description for your reference -
 

Job Description: 

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.