Target Job Titles: Senior Embedded Systems Engineer (Lead Technical Translator) Position Type: Remote Part-Time Contract (10–15 hours/week) during Phase I feasibility, with direct full-time conversion to Chief Technology Officer (CTO) upon Phase II prototype authorization. Security Clearance: U.S. Citizenship Required; Clearable for DoD Secret Clearance
Company Overview
We are an agile, patent-backed, minority-owned defense technology startup focused on cutting-edge autonomous swarm defense. Our entity is actively positioning for a highly leveraged $1,000,000 Phase I capitalization posture (combining federal Phase I R&D funding, pre-arranged private seed placement, and state-level dollar-for-dollar matching programs). We are seeking a high-cognitive technical wordsmith to serve as our lead proposal architect for upcoming Army SBIR topic ARM26BX04-NV008.
Position Summary We are seeking a master craftsman of bare-metal firmware to serve as our Lead Technical Translator. You will take our foundational mathematical proofs and map them onto a physical, hardware-in-the-loop (HWIL) constraints framework. You must be comfortable working entirely without hardware floating-point units (FPUs), designing systems that enforce absolute mathematical determinism in communication-denied environments.
Core Responsibilities • Translate proprietary utility patent mathematics (including integer-scaled Markov state transition probability matrices) into strict 16.16 signed fixed-point integer registers. • Architect the firmware execution loop to utilize 256-byte static trigonometric lookup tables to resolve coordinate rotations natively within single-cycle ALU constraints. • Configure hardware-driven Non-Maskable Interrupt (NMI) pin lines and memory-mapped digital sensing lines to trigger atomic register overwrites within a 3-clock-cycle window. • Provide a verifiable resume and sign a contingent Letter of Intent (LOI) to satisfy federal personnel verification gates.
Required Qualifications • Experience: 5+ years of bare-metal C/C++ and Assembly development targeting low-gate-count, supply-chain-secure microcontrollers (ARM Cortex-M, RISC-V, or automotive-grade silicon). • Technical Focus: Expert-level understanding of fixed-point math, integer register partitioning, hardware interrupt behaviors, and passive sensory interfaces (CMOS optical flow, SWIR stellar tracking). • Industry Background: Direct experience with UAV flight controllers, robotic kinematics, or guidance/navigation/control (GNC) systems.