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Remote Cold Forming Tool Design Engineer Jobs in Riverside, CA

Saratech

Design Solutions COE

Mission Viejo, CA · Remote

$77K - $105K/yr

Position is remote but may require occasional travel.Create and/or update mechanical CAD models ... Identify engineering problems and ensure optimal solutions are implemented.Work with the Technical ...

First American

Senior Software Engineer

Santa Ana, CA · On-site +1

$127K - $168K/yr

What We Do Remote Work Welcome Be part of a transformative team that is shaping the way First ... We are looking for forward-thinking engineers who will envision, design, build, and deploy AI ...

Saratech

Electrical Engineer

Mission Viejo, CA · Remote

... D tool (e.g., Visual Engineer, AutoCAD Electrical, Capital Harness)Understanding of both digital and analog electrical interfaces, including voltage drop, timing, and signal integrity ...

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All JobsCold Forming Tool Design Engineer JobsRemote Cold Forming Tool Design Engineer JobsRemote Cold Forming Tool Design Engineer Jobs in Riverside, CA

Remote Cold Forming Tool Design Engineer information

See Riverside, CA salary details

$55.8K

$94.4K

$139.3K

How much do remote cold forming tool design engineer jobs pay per year?

As of Sep 2, 2026, the average yearly pay for remote cold forming tool design engineer in Riverside, CA is $94,362.00, according to ZipRecruiter salary data. Most workers in this role earn between $76,200.00 and $107,500.00 per year, depending on experience, location, and employer.

What is the difference between Remote Cold Forming Tool Design Engineer vs Remote Die Design Engineer?

AspectRemote Cold Forming Tool Design EngineerRemote Die Design Engineer
Primary FocusDesigning tools for cold forming processesDesigning dies for various manufacturing processes
Required SkillsTool design, materials, cold forming techniquesDie design, CAD, manufacturing methods
Work EnvironmentManufacturing, engineering firms, remote optionsManufacturing, engineering, remote roles
Industry UsageAutomotive, aerospace, fastenersAutomotive, machinery, metalworking

Both roles involve designing components for manufacturing, often requiring CAD skills and industry-specific knowledge. The main difference lies in the focus: Cold Forming Tool Design Engineers specialize in tools for cold forming processes, while Die Design Engineers focus on die components for various manufacturing methods. Both roles are essential in manufacturing sectors and can be performed remotely, depending on the employer.

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For Remote Cold Forming Tool Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:

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Remote Cold Forming Tool Design Engineer jobs near you

Design Verification Engineer - Remote - Contract opportunity

Zodiac Solutions

Irvine, CA • Remote

$139K - $169K/yr

Contractor

Re-posted 10 days ago

Job description

Role – Design Verification Engineer

Location – Remote (must be aligned with PST time zone)

Duration- Contract opportunity

 Job Description and other details –

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.