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Remote Asic Design Engineer Jobs in New York (NOW HIRING)

Ambrook

Design Engineer

New York, NY · On-site +1

$115K - $280K/yr

  • Medical

  • Retirement

  • PTO

Sitting at the center of design and engineering, you work well across disciplines to get things ... Work-from-home/remote office stipend * Wellness stipend * Professional development stipend Our ...

Salas O'Brien

Security Systems Design Engineer

Monroe, NJ · On-site +1

$105K - $130K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Security Systems Design Engineer At Salas O'Brien we tell our clients that we're engineered for ... New Jersey or New York (HYBRID) Or REMOTE Travel : Some travel to US sites. Compensation & Benefits:

Mercor

Product Design Expert - Vibecoding

New York, NY · Remote

$70 - $80/hr

Remote Role Responsibilities * Construct scenarios spanning rapid prototyping, design system development, and cross-functional product-design-engineering collaboration. * Build tasks across AI ...

Mercor

Mechanical Design PhD - CAD Expert

New York, NY · Remote

$85/hr

Position: CAD / Mechanical Design Writer - Engineering FRQ Type: Contract Compensation: $85/hour ... Remote Role Responsibilities * Author original, free-response engineering problems grounded in real ...

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Remote Asic Design Engineer information

What is a remote ASIC design engineer?

A Remote ASIC Design Engineer is a professional who designs Application-Specific Integrated Circuits (ASICs) while working remotely, often from home or another location outside of a traditional office. They are responsible for creating and verifying digital or analog circuit designs tailored to specific applications, such as telecommunications, automotive, or consumer electronics. These engineers use specialized hardware description languages (HDLs) like Verilog or VHDL and collaborate with teams using online tools for simulation, synthesis, and verification. Remote ASIC Design Engineers must have strong technical skills and the ability to communicate and coordinate effectively in a virtual work environment.

What are the key skills and qualifications needed to thrive as a remote ASIC design engineer?

To thrive as a Remote ASIC Design Engineer, you need a solid background in digital circuit design, Verilog or VHDL programming, and a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as experience in simulation, synthesis, and verification processes, is typically required. Strong problem-solving skills, effective communication, and the ability to collaborate virtually are standout soft skills for remote success. These competencies ensure efficient design cycles, high-quality deliverables, and seamless teamwork in distributed engineering environments.

What are some common challenges faced by remote ASIC design engineers, and how can they be effectively managed?

Remote ASIC Design Engineers often encounter challenges such as coordinating across multiple time zones, ensuring effective communication with hardware and verification teams, and maintaining access to high-performance computing resources. To overcome these hurdles, it’s essential to use collaborative project management tools, establish clear communication protocols, and schedule regular sync meetings. Additionally, many companies provide secure remote access to lab resources and simulation tools, helping engineers stay productive and connected with their teams.

What is the difference between Remote Asic Design Engineer vs Remote FPGA Design Engineer?

AspectRemote Asic Design EngineerRemote FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experienceBachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experience
Work EnvironmentDesigning integrated circuits for manufacturing, often in semiconductor companiesDeveloping programmable logic designs, often in research or product development teams
Industry UsageSemiconductor, consumer electronics, automotiveTelecommunications, aerospace, embedded systems

Both roles require similar educational backgrounds and design experience, but the Remote Asic Design Engineer focuses on creating chips for mass production, while the Remote FPGA Design Engineer works on programmable logic devices. Their work environments and industry applications differ, aligning with their specific design goals.

What are the most commonly searched types of Asic Design Engineer jobs in New York?

The most popular types of Asic Design Engineer jobs in New York are:

What are popular job titles related to Remote Asic Design Engineer jobs in New York?

For Remote Asic Design Engineer jobs in New York, the most frequently searched job titles are:

What job categories do people searching Remote Asic Design Engineer jobs in New York look for?

The top searched job categories for Remote Asic Design Engineer jobs in New York are:

What cities in New York are hiring for Remote Asic Design Engineer jobs?

Cities in New York with the most Remote Asic Design Engineer job openings:

Remote Asic Design Engineer jobs near you

Load Balancer Design Engineer - Remote

Apetan Consulting llc

Jersey City, NJ • Remote

$80 - $150/hr

Contractor

Re-posted 27 days ago

Job description

Job Description: Load Balancer Design Engineer – Remote

 

Load Balancer Design Engineer for a 1 year W2 contract (with possibility of extension) position that is remote. This role focuses on architecture, design, lifecycle management, and optimization of load balancing platforms including F5 and VMware AVI. The engineer will drive scalable, secure, and resilient solutions aligned with enterprise standards and business requirements.

 

Load Balancer Design Engineer job responsibilities include:

·        Manage end-to-end lifecycle of application delivery infrastructure including design, deployment, upgrades, and decommissioning

·        Design solutions based on industry best practices, engineering standards, and security principles

·        Develop High-Level Designs (HLDs), Low-Level Designs (LLDs), runbooks, and implementation plans

·        Architect application delivery including SSL offloading, DNS, persistence, traffic optimization, and security controls

·        Ensure security controls and compliance requirements are embedded into all designs

·        Perform QA validation and testing to ensure successful production deployment

·        Collaborate with global engineering, operations, and LOB teams for service transition and delivery

·        Drive service request fulfillment processes and improve operational efficiency

·        Reduce change incidents through peer reviews, standardized deployment, and governance

·        Lead lifecycle programs including patching, upgrades, vulnerability remediation, and EOL replacement

·        Provide metrics reporting and present insights to leadership

·        Troubleshoot complex load balancing, DNS, SSL, and network issues in production environments

 

 

Qualifications:

·        5–8+ years of experience in network engineering with strong focus on load balancing and application delivery

·        Hands-on expertise in F5 LTM and GTM

·        Experience with F5 APM and ASM modules

·        Exposure to VMware AVI (NSX Advanced Load Balancer)

·        Strong understanding of protocols including TCP/IP, HTTPS, BGP, DNS, and SSL/TLS

·        Deep knowledge of application switching, traffic management, persistence, and optimization

·        Experience with SSL offloading, certificate lifecycle, and PKI processes

·        Strong troubleshooting skills in large, complex environments

·        Experience working with APIs such as F5 iControl for automation and integration

·        Ability to design scalable, secure, and highly available infrastructures

·        Excellent communication and stakeholder management skills

·        Ability to interact with cross-functional teams and business stakeholders

·        Minimum 3 years F5 Load Balancing experience

·        Working knowledge of AVI Load Balancing (legacy platform)

·        Experience in a life cycle management technology refresh program.