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Random Jobs in Austin, TX (NOW HIRING)

ASIC Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Constrained Random Verification (CRV) * Functional Coverage & Coverage Closure * RTL Debug & ASIC/SoC Verification Key Responsibilities * Develop UVM/SystemVerilog verification environments. * Create ...

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As of Aug 8, 2026, the average hourly pay for random in Austin, TX is $23.37, according to ZipRecruiter salary data. Most workers in this role earn between $18.12 and $26.20 per hour, depending on experience, location, and employer.

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Infographic showing various Random job openings in Austin, TX as of August 2026, with employment types broken down into 73% Full Time, 21% Part Time, and 6% Contract. Highlights an 96% In-person, and 4% Remote job distribution, with an average salary of $48,611 per year, or $23.4 per hour.

Sr. Asic Design Verification Engineer

VentureSoft Global

Austin, TX โ€ข On-site

$134K - $164K/yr

Other

Posted 16 days ago


Job description

Job Title: Senior ASIC Design Verification Engineer
Location: Austin, TX (Onsite/Hybrid)
Experience: 15+ Years
Job Summary
We are seeking an experienced Senior ASIC Design Verification Engineer to verify next-generation CPU, AI/ML, and SoC designs. The ideal candidate will have strong expertise in developing UVM-based verification environments, functional coverage, RTL debug, and constrained-random verification while working closely with design and architecture teams from specification through tape-out.
Primary Skills (Must Have)
  • SystemVerilog & UVM
  • Constrained Random Verification (CRV)
  • Functional Coverage & Coverage Closure
  • RTL Debug & ASIC/SoC Verification
Key Responsibilities
  • Develop UVM/SystemVerilog verification environments.
  • Create test plans, testbenches, sequences, scoreboards, and checkers.
  • Perform block-level and full-chip ASIC/SoC verification.
  • Execute constrained-random and directed testing.
  • Debug RTL issues and drive functional coverage closure.
  • Collaborate with design, architecture, and validation teams.
  • Support regression, verification signoff, and tape-out activities.
Preferred Skills
  • CPU/Processor or Memory Subsystem Verification
  • SVA (SystemVerilog Assertions)
  • ARM, RISC, AI/ML Accelerator, or GPU verification
  • Experience with VCS, Questa, or Xcelium
  • Python or C/C++
Education
Bachelor''s or Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.