Job Descriptionย
We are looking for a Principal Design Verification Engineerwith proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.ย
Basic Qualifications:ย
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE isย
required, and a Maser's is preferred.ย - 8ย years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/orย
Networking applications.ย - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare forย
customer meetings in advance, and to work with minimal guidance and supervision.ย - Entrepreneurial, open-mindbehavior and can-do attitude. Think and act fast with the customer in mind!ย
- Authorized to work in Canada and startimmediately.ย
Required Experience:
- Experience with integrating C/C++ in System Verilog environments using DPI/PLIย
- Ability to use scripting tools (Perl/Python) to automate verification infrastructure.ย
- Experience in developing infrastructure and tests in a hybrid directed and constrained randomย
environmentsย - Must be able to work independently to develop test-plans, and related test-sequences in UVM toย
generate stimuli and work collaboratively with RTL designers to debug failures.ย - Develop user-controlled random constraints in transaction-based verificationmethodology. Experienceย
writing assertions, cover properties and analyzing coverage dataย - Must have prior experience using Verification IPs from 3rd party vendors for communication protocolsย
such as PCI-Express (Gen-3 and above), Ethernet,Infiniband, DDR,NVMe, USB, etc.ย - Develop VIP abstraction layers to simplify and scale verification deploymentsย
Preferred Experience:
- S/W debugging for SoC based designsin the area ofkernel/device-drivers/u-bootย
- Physical Layer, Link Layer and Transaction Layer verificationexpertisein PCIe protocol.ย
- Experience in memory technologies like DDR4/DDR5/HBM.ย
- Experience with FPGA-based verification/emulation.ย
Base salary range is $165,000 CAD -$210,000 CAD, and will be determined based on the candidate's capabilities and employees in similar positions.ย