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Process Reliability Manager Jobs in Alameda, CA (NOW HIRING)

Ayar Labs

Principal Engineer, Reliability

San Jose, CA · On-site

$120K - $151K/yr

Define and drive wafer-level reliability (WLR) structures and test vehicles to characterize new photonics and mixed-signal EIC process nodes. * Manage reliability requirements for advanced packaging ...

New

Meta

Reliability Engineer

Sunnyvale, CA

$144K/yr

... process, and use-condition contributors * Define and track reliability KPIs, including MTBF ... Engage cross-functional stakeholders, including product management, quality, and operations, to ...

Waymo

Staff Hardware Reliability Engineer

Mountain View, CA · On-site

$120K - $152K/yr

Experience in managing the DFMEA or other risk analysis process across a product line. * Extensive experience developing comprehensive reliability test plans, resolving complex failure analyses, and ...

OSI Engineering

Reliability Engineering Lead

Palo Alto, CA · On-site

$300K - $400K/yr

Drive Design for Reliability (DfR) throughout the development process by leading FMEA reviews ... Experience managing external reliability labs, certification partners, and contract manufacturers.

Waymo

Staff Hardware Reliability Engineer

Mountain View, CA · On-site

$210K - $259K/yr

Experience in managing the DFMEA or other risk analysis process across a product line. * Extensive experience developing comprehensive reliability test plans, resolving complex failure analyses, and ...

Ayar Labs

Photonics Reliability Architect

San Jose, CA · On-site

$170 - $200/hr

Collaborate closely with design and process engineering teams to integrate reliability principles ... Prepare detailed reliability reports, present findings to cross‑functional teams and management ...

Cisco

Reliability Engineering Technical Leader

San Jose, CA · On-site

$162K - $205K/yr

... management (PLM) strategies, improve operational efficiency, and drive innovation and transformation across NPI, sustaining, and end-to-end supply chain processes. Your Impact As a Reliability ...

Cisco

Reliability Engineering Technical Leader

San Jose, CA · Hybrid

$162K - $205K/yr

... management (PLM) strategies, improve operational efficiency, and drive innovation and transformation across NPI, sustaining, and end-to-end supply chain processes. Your Impact As a Reliability ...

Meta

Reliability Engineer, Hardware

Sunnyvale, CA

$173K/yr

... process, and use-condition contributors * Define and track reliability KPIs, including MTBF ... Engage cross-functional stakeholders, including product management, quality, and operations, to ...

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All JobsProcess Reliability JobsProcess Reliability Manager JobsProcess Reliability Manager Jobs in Alameda, CA

Process Reliability Manager information

See Alameda, CA salary details

$70.3K

$133.2K

$191K

How much do process reliability manager jobs pay per year?

As of Sep 4, 2026, the average yearly pay for process reliability manager in Alameda, CA is $133,156.00, according to ZipRecruiter salary data. Most workers in this role earn between $107,100.00 and $158,700.00 per year, depending on experience, location, and employer.

What is a process reliability manager?

A Process Reliability Manager is a professional responsible for ensuring that manufacturing or production processes operate efficiently, consistently, and with minimal downtime. They analyze process data, identify areas for improvement, and implement strategies to enhance equipment reliability and overall process performance. By collaborating with maintenance, engineering, and operations teams, they help reduce failures, optimize productivity, and maintain quality standards. Their work is crucial for minimizing costs and ensuring that production targets are met safely and reliably.

What are the key skills and qualifications needed to thrive as a process reliability manager, and why are they important?

To thrive as a Process Reliability Manager, you need a strong background in engineering, process optimization, and reliability analysis, often supported by a degree in engineering and experience in manufacturing or industrial settings. Familiarity with reliability-centered maintenance (RCM), root cause analysis tools, and data analysis software such as SAP or Maximo is typically required. Exceptional problem-solving, leadership, and communication skills help drive cross-functional teams and foster a culture of continuous improvement. These skills are crucial to ensure equipment reliability, minimize downtime, and optimize operational efficiency within complex production environments.

How does a process reliability manager typically collaborate with maintenance and production teams to achieve operational goals?

A Process Reliability Manager works closely with both maintenance and production teams to identify areas of improvement in equipment reliability and process efficiency. This often involves facilitating cross-functional meetings, analyzing downtime data, and implementing preventive maintenance strategies. Clear communication and teamwork are key, as the role requires aligning the objectives of different departments to minimize unplanned outages and optimize production output. By fostering a proactive culture and sharing best practices, the Process Reliability Manager helps ensure the plant operates smoothly and efficiently.

What is the difference between Process Reliability Manager vs Maintenance Engineer?

AspectProcess Reliability ManagerMaintenance Engineer
CertificationsReliability certifications, Six Sigma, PMPMechanical/Electrical certifications, HVAC, PLC certifications
Work EnvironmentManufacturing plants, industrial facilitiesFactories, equipment maintenance sites
Industry UsageFocus on reliability, uptime, and process optimizationFocus on equipment repair, preventive maintenance

The Process Reliability Manager primarily focuses on improving equipment reliability and process efficiency through data analysis and strategic planning. In contrast, Maintenance Engineers handle the hands-on repair and maintenance of machinery. Both roles are essential in manufacturing, but the Process Reliability Manager emphasizes proactive reliability strategies, while Maintenance Engineers focus on reactive and preventive maintenance tasks.

What cities near Alameda, CA are hiring for Process Reliability Manager jobs?

Cities near Alameda, CA with the most Process Reliability Manager job openings:

Process Reliability Manager jobs near you

Principal Engineer, Reliability

Ayar Labs

San Jose, CA • On-site

$120K - $151K/yr

Full-time

Posted yesterday

New

Job description

Principal Engineer, Reliability
Location: San Jose (on-site)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

In this high-impact leadership role, you will be the primary architect of the reliability roadmap spanning our silicon photonics platform and the mixed-signal EICs that drive it. You will bridge the gap between R amp;D and high-volume manufacturing, ensuring that our optical I/O solutions — PIC and EIC together — exceed the stringent requirements of the world’s leading AI and data center customers. Your expertise will directly influence chiplet co-design, foundry process qualification, and system-level reliability at the PIC-EIC interface.

Key Responsibilities
  • Product Qualification amp; Corrective Action follow up
    • Own the execution and plan for the production qualification products, which includes silicon photonics and mixed-signal EIC components. Complying with JEDEC, Telcordia (GR-468), and MIL-STD standards..
    • Develop corrective action plans (CAPA) to resolve reliability issues discovered during qualification or in-field deployment, partnering with failure analysis, operation and design teams as needed.
  • Design for Reliability (DfR) — PIC and EIC
    • Integrate DfR principles into the earliest stages of the product development lifecycle (NPI) for both the photonics chiplet and its mixed-signal EIC.
    • Conduct Failure Mode and Effects Analysis (FMEA) across the PIC-EIC system, covering optical elements (waveguides, ring resonators, modulators, photodetectors) and mixed-signal circuit blocks (drivers, TIAs, ADC/DAC, control loops).
    • Collaborate with photonics design, analog/mixed-signal IC design, and layout teams to implement design-based mitigations for known failure mechanisms, including electromigration, dielectric breakdown, hot-carrier injection, NBTI/PBTI, and optical degradation.
    • Define reliability guardbands and design rules at the PIC-EIC interface (co-packaged optics), where electrical and optical degradation modes interact.
  • Foundry amp; Ecosystem Reliability
    • Serve as the technical lead for reliability with foundry partners across both silicon photonics and CMOS/mixed-signal process nodes, ensuring their processes meet Ayar Labs’ quality benchmarks.
    • Define and drive wafer-level reliability (WLR) structures and test vehicles to characterize new photonics and mixed-signal EIC process nodes.
    • Manage reliability requirements for advanced packaging and Co-Packaged Optics (CPO) with OSAT partners, covering both optical and electrical interconnects.
  • Advanced Reliability Modeling
    • Develop and refine Physics-of-Failure (PoF) models for silicon photonics devices and mixed-signal EIC circuits to predict FIT (Failures in Time) rates and DPPM.
    • Utilize statistical software (JMP, Minitab, or Python) to perform Weibull and Lognormal analysis on accelerated life testing (ALT) and degradation data for both PIC and EIC populations.
    • Model the impact of environmental stressors — thermal cycling, humidity, high-power optical loads, and electrical stress — on the long-term performance of the combined photonics-EIC system.
    • Build unified reliability degradation and margin models that capture the interaction between optical link margin and EIC circuit aging.

Required Qualifications
  • Education: Bachelor’s degree in Electrical Engineering, Physics, Materials Science, or a related field.
  • Experience: 10+ years of semiconductor reliability experience, with at least 5 years focused specifically on Silicon Photonics and/or Mixed-Signal EIC reliability.
  • Mixed-Signal: Working knowledge of mixed-signal IC design and the reliability mechanisms unique to it (electromigration, HCI, NBTI/PBTI, ESD, latch-up) in addition to photonics-specific mechanisms.
  • Foundry Knowledge: Deep understanding of foundry process flows and the reliability challenges unique to photonics and CMOS/mixed-signal processes, including optical power handling, aging, and thermal management in CPO.
  • Modeling Mastery: Proven track record developing aging models (Arrhenius, Coffin-Manson, etc.) for semiconductor and photonic devices.
  • Standards Expertise: Familiarity with JEDEC, Telcordia (GR-468), and MIL-STD qualification standard and the Physics behind these requirements
  • Computer skills: Proficiency in using Phyton to control lab equipment and DUT

Preferred Qualifications
  • Education: PhD or Master’s degree in Electrical Engineering, Physics, Materials Science, or a related field.
  • PhD degree with 15+ years of relevant experience
  • Hands-on experience with Python for automated reliability data pipelines.
  • Prior experience co-qualifying an optical chiplet alongside its companion EIC in a co-packaged optics (CPO) architecture.
  • Demonstrated leadership experienceExperience in reliability issues with advanced silicon technologies (7
  • 3nm), advanced packaging (CPO/COWOS) and FAU reliability
  • Direct external customer interaction experience
Salary range: $200,000 - $260,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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