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Principal Design Verification Engineer Jobs (NOW HIRING)

SiFive, Inc.

WI · On-site

$150 - $200/hr

## Principal Design Verification Engineer - CPU Subsystem Power ManagementApplylocations: Austin, Texas, United States: Santa Clara, California, United Statestime type: Full timeposted on: Posted ...

Renesas Electronics Corporation

$200 - $250/hr

Position Overview Renesas is seeking an experienced Principal Verification Engineer to lead the ... Design and architect mixed-signal verification environments, including Real Number Model (RNM) and ...

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How much do principal design verification engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for principal design verification engineer in the United States is $147,220.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,500.00 and $173,000.00 per year, depending on experience, location, and employer.

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For Principal Design Verification Engineer jobs, the most frequently searched job titles are:

(Principal/Lead) SoC Design Verification Engineer (Sunnyvale)

Sunnyvale, CA • On-site

Thrive Recruitment Agency
See more jobs at Thrive Recruitment Agencyexternal

$160K - $195K/yr

Full-time

Re-posted 4 days ago

Job description

(Principal/Lead) SoC Design Verification Engineer

Job Openings (Principal/Lead) SoC Design Verification Engineer

About the job (Principal/Lead) SoC Design Verification Engineer

As a SoC Design Verification Lead, you will be responsible to lead the DV effort for Celestial AI/ML SoC. You will be responsible for verification execution, driving efficiencies in verification strategy for an SoC from pre-silicon simulation through post-silicon validation and through the SoC production

You would have organizational leadership experience in supporting high-performance teams and processes, be a strategic problem-solver with demonstrated collaboration and communication skills.

Responsibilities
  • Lead DV effort to define and review verification and validation testplans at block, IP and SoC
  • Build, manage and mentor a team of ASIC/SoC verification engineers including managing external verification contractors/consultants.
  • Work with ASIC/SoC design team to manage critical milestones and deliveries
  • Work with Architecture, Design and Verification technical leads to shape the SoC verification methodologies and processes and to ensure DV reusability
  • Work with software team to validate complete tool chain including running real world use cases on verification models
  • Create coverage driven verification plans from specification, review and refine to achieve coverage targets
  • Provide technical leadership through mentorship and strong teamwork
Requirements
  • Natural leader who enjoys working with hardware and software development teams
  • Excellent organization skills to prioritize requirements.
  • Experience in pre-silicon verification with developing and maintaining complex SoC design verification environments in OVM, UVM and System Verilog -experience with High Level Synthesis and System C preferred
  • Hands-on experience in execution of verification plans
  • Successful tapeout of IP, CPU, GPU, AI/ML or any complex SoC development highly desirable.
  • Prior verification experience in PCIe, on-chip memory, ARM AXI, APB protocols and on-chip NOC
  • Experience in Python and scripting.
  • Team player that proactively engages with cross functional engineering teams.
  • Experience working with and directing external contractors and verification consultants
  • BSEE + 6 years of relevant design verification and management experience
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