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Principal Analog Design Engineer Jobs (NOW HIRING)

TylSemi

Principal Analog Design Engineer

San Jose, CA · On-site

$175K - $350K/yr

Role Overview As an Analog Design Engineer at Tylsemi, you will design and deliver high-performance analog and mixed-signal circuits that enable robust, manufacturable silicon. This role spans a wide ...

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Principal Analog Design Engineer information

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$74K

$147.2K

$212.5K

How much do principal analog design engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for principal analog design engineer in the United States is $147,220.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,500.00 and $173,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a principal analog design engineer, and why are they important?

To thrive as a Principal Analog Design Engineer, you need deep expertise in analog circuit design, device physics, and a relevant engineering degree, often with extensive industry experience. Mastery of simulation tools like Cadence, SPICE, and familiarity with IC layout and verification methodologies are typically required, along with relevant certifications or training. Strong problem-solving, leadership, and communication skills set top candidates apart by enabling effective project management and cross-functional collaboration. These skills ensure reliable, innovative analog solutions that meet complex technical requirements and drive project success.

What does a principal analog design engineer do?

A Principal Analog Design Engineer leads the design and development of analog and mixed-signal integrated circuits (ICs) for various applications such as communications, consumer electronics, and automotive systems. They are responsible for overseeing complex circuit design projects, mentoring junior engineers, and ensuring that the designs meet performance, reliability, and manufacturing requirements. Their work often involves simulation, layout supervision, and close collaboration with cross-functional teams throughout the product development cycle.

What is the difference between Principal Analog Design Engineer vs Analog Design Engineer?

AspectPrincipal Analog Design EngineerAnalog Design Engineer
Required CredentialsBachelor's/Master's/PhD in Electrical Engineering, extensive experienceBachelor's or Master's in Electrical Engineering, some experience
Work EnvironmentLeading design projects, mentoring teams, strategic planningDesigning analog circuits, testing, and implementation
Employer & Industry UsageSemiconductor companies, high-tech firms, R&D departmentsConsumer electronics, communication, automotive industries

The Principal Analog Design Engineer typically holds more experience and leadership responsibilities, focusing on project direction and mentorship. In contrast, the Analog Design Engineer primarily executes circuit design and testing tasks. Both roles require strong technical skills, but the principal position involves strategic oversight and higher-level decision-making.

What are some common challenges faced by principal analog design engineers in leading complex projects?

Principal Analog Design Engineers often encounter challenges such as balancing performance specifications with power and area constraints, managing signal integrity issues, and ensuring design robustness across process variations. They are also responsible for coordinating multidisciplinary teams, including layout engineers and verification specialists, to align on project goals and timelines. Effective communication and problem-solving skills are essential to address unforeseen design issues and to mentor junior engineers throughout the project lifecycle.
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Infographic showing various Principal Analog Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% Internship, 87% Full Time, 7% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $147,220 per year, or $70.8 per hour.

Principal Analog Design Engineer

TylSemi

San Jose, CA • On-site

$175K - $350K/yr

Full-time

Re-posted 11 days ago

Job description

Role Overview
As an Analog Design Engineer at Tylsemi, you will design and deliver high-performance analog and mixed-signal circuits that enable robust, manufacturable silicon. This role spans a wide experience range (5-30 years) and is ideal for engineers who combine strong fundamentals with practical execution-translating system requirements into silicon-ready designs, validating performance across corners, and partnering closely with layout, verification, test, and product teams to drive first-time-right outcomes.
What You'll Do
  • Own end-to-end analog block development: requirements definition, architecture, transistor-level design, simulation, and signoff
  • Design and optimize analog/mixed-signal circuits such as amplifiers, references, biasing, regulators (LDO/DC-DC support), comparators, oscillators/clocking, data converters (as applicable), and sensor/AFE front ends
  • Drive performance across PVT corners, mismatch/Monte Carlo, aging/reliability considerations, and realistic loading/interaction with surrounding blocks
  • Partner with layout to guide floorplanning, matching/guarding strategies, parasitic-aware design, and post-layout closure (PEX)
  • Develop and maintain testbenches, modeling collateral, and documentation to enable efficient verification and integration
  • Support silicon bring-up and debug: correlate lab data to simulations, root-cause issues, and implement design fixes or ECOs
  • Collaborate cross-functionally with digital, firmware, DFT, validation, and product engineering to ensure system-level success
  • Contribute to design methodology improvements: reusable circuits, checklists, signoff flows, and best practices that scale across programs

What We're Looking For
  • 5+ years of experience in analog or mixed-signal IC design (scope and ownership aligned to experience level)
  • Strong fundamentals in analog circuit design, device physics, noise, stability/compensation, and feedback systems
  • Proficiency with industry-standard EDA tools and simulation flows (e.g., Spectre/HSPICE, ADE, waveform/debug tooling)
  • Experience closing designs through post-layout parasitics and across process/voltage/temperature corners
  • Ability to translate ambiguous system needs into clear block requirements and executable design plans
  • Strong debugging skills and comfort working with lab/validation teams to correlate silicon to simulation
  • Clear communication and high ownership in cross-site, cross-functional environments

Nice to Have
  • Experience with high-speed or precision analog (low-noise, low-offset, high-linearity) depending on product needs
  • Background in power management (LDOs, bandgaps, references, protection, start-up, transient response)
  • ADC/DAC, Power related analog experience
  • Familiarity with reliability/ESD considerations and design-for-manufacturability practices
  • Experience supporting production ramp: yield learning, characterization, and test correlation

Success in This Role Looks Like
  • Analog blocks meet spec with margin across PVT, mismatch, and post-layout effects
  • Design reviews are crisp: requirements, tradeoffs, and risks are clearly articulated and managed
  • Silicon bring-up converges quickly through strong correlation, structured debug, and decisive fixes
  • Cross-functional partners (layout, verification, test, validation) can execute efficiently with clear interfaces and documentation
  • Reusable design collateral and improved methodology reduce cycle time and increase first-pass success

About TylSemi, Inc.
The Opportunity
The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?
That's what we solve. TylSemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.
This isn't a nice-to-have. It's the critical path.
Why Now
The Market Window
The semiconductor industry is going through its biggest architectural shift in 40 years:
• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.
Culture & Team: How We Work
No Politics, No Bureaucracy
There are no layers, no approval chains, no corporate theater.
• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.
Remote-Friendly, Global Team
• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore
Move Fast, Ship Real Products
We're not a research project. We have paying customers, committed capital, and aggressive timelines.
This is a company, not a lifestyle business. We're building to win.
What We Value
• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.
The Ask
If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.
We're asking you to walk away from that and bet on us.
Here's why you should:
• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.
This is the bet. Join us and build something that matters.
Or stay comfortable. No judgment.
But if you're the kind of person who wants to take the shot, we'd love to talk.
READY TO JOIN?
The pay range for this role is:
175,000 - 350,000 USD per year (San Jose (HQ))

Apply