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Power Management Ic Design Engineer Jobs (NOW HIRING)

Qorvo's fast-growing Power Management division is at the forefront of innovation in Power Loss ... We are seeking a highly skilled Analog Power Design Engineer to develop next-generation, high ...

Timing closure of the blocks with best PPA (power/performance/area) * Debug LVS/DRC/ERC errors with ... Collaborate with design and layout engineers to optimize layout for area and performance * Work ...

Principal Design Engineer, Nexperia USA Inc., Richardson, TX: Work with an analog and mixed signal IC design team to develop power management products like switching regulators, load switches, and ...

New

Timing closure of the blocks with best PPA (power/performance/area) * Debug LVS/DRC/ERC errors with ... Collaborate with design and layout engineers to optimize layout for area and performance * Work ...

Design for ESD compliance. Minimum Qualifications Bachelor's of Science in Electric Engineering ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Design for ESD compliance. Minimum Qualifications Bachelor's of Science in Electric Engineering ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...

Timing closure of the blocks with best PPA (power/performance/area) * Debug LVS/DRC/ERC errors with ... Collaborate with design and layout engineers to optimize layout for area and performance * Work ...

Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register ... Low-power serial link MAC/PHY * Design and optimization of hardware/software interface with ...

Analog Design Engineer

San Diego, CA · On-site

$80K - $125K/yr

Power efficient and high precision design * Support IC characterization and test development to ... power management circuits * Experience with high-voltage (100V+) or mixed-voltage designs with ...

Showing results 41-60

Power Management Ic Design Engineer information

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$40.5K

$88.2K

$158.5K

How much do power management ic design engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for power management ic design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What does a power management IC design engineer do?

A Power Management IC (Integrated Circuit) Design Engineer is responsible for designing and developing integrated circuits that manage the distribution and regulation of electrical power in electronic devices. Their work involves creating circuits that optimize power efficiency, regulate voltage, and protect against power-related issues like surges or overheating. They use specialized software for circuit simulation and layout, collaborate with cross-functional teams, and ensure that their designs meet the required performance, safety, and reliability standards. These engineers play a critical role in industries such as smartphones, computers, automotive electronics, and IoT devices.

What are the key skills and qualifications needed to thrive as a power management IC design engineer?

To thrive as a Power Management IC Design Engineer, you need a solid background in analog/mixed-signal circuit design, semiconductor physics, and a relevant degree in electrical or electronics engineering. Experience with EDA tools like Cadence, SPICE simulation software, and familiarity with industry standards are typically required, along with possible certifications in IC design. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help distinguish top performers in this field. These competencies are crucial for designing efficient, reliable power management solutions that meet stringent technical and commercial requirements.

What are some common challenges faced by power management IC design engineers during the development cycle?

Power Management IC Design Engineers often face challenges such as balancing high efficiency with low quiescent current, managing thermal performance, and ensuring robust operation under varying loads. They must also address complex integration with other analog and digital blocks, requiring close collaboration with layout, verification, and system engineers. Tight project timelines and the need to meet stringent industry standards can add additional pressure, making effective communication and problem-solving skills essential for success.

What are popular job titles related to Power Management Ic Design Engineer jobs?

For Power Management Ic Design Engineer jobs, the most frequently searched job titles are:

Staff Analog IC Design Engineer

San Jose, CA • Hybrid

Qorvo, Inc.
Manufacturing • 5 - 10K employees

$144K - $187K/yr

Full-time

Posted 14 days ago


Qorvo rating

8.3

Company rating: 8.3 out of 10

Based on 21 frontline employees who took The Breakroom Quiz


Job description

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.

Qorvo's fast-growing Power Management division is at the forefront of innovation in Power Loss Protection, PMICs, Motor Control, and Battery Management solutions, serving a diverse range of applications across Mobile, Consumer, IoT, and Industrial markets. We are seeking a highly skilled Analog Power Design Engineer to develop next-generation, high-performance power management solutions. In this role, you will drive architecture, design, and validation of industry-leading analog power ICs, collaborating closely with cross-functional global teams to deliver world-class products that set new benchmarks in efficiency, reliability, and performance.

This is a hybrid position where the expectation is to be onsite multiple days a week at either our Richardson TX or San Jose CA office. 

Responsibilities:

  • Lead the design and development of high-performance analog power management ICs, ensuring best-in-class efficiency, power density, and reliability.
  • Collaborate with system engineers to define product architecture and specifications, balancing performance, power, and cost requirements.
  • Select and implement optimal circuit topologies, ensuring robustness, yield, and manufacturability.
  • Conduct transistor-level design, simulation, and validation to meet functional and performance specifications.
  • Work closely with layout engineers to optimize floor planning, parasitic, and overall silicon performance.
  • Engage with global design teams, including colleagues in Asia, to align on development strategies and execution plans.
  • Partner with test and characterization engineers to define validation methodologies, troubleshoot design issues, and optimize production test strategies.
  • Drive technical reviews and documentation, presenting design decisions, analysis, and trade-offs to internal stakeholders.

Required Qualifications:

  • A minimum of a Bachelor's degree in Electrical Engineering
  • 8+ years of engineering experience (or an equivalent amount of education and expereince) working in the semiconductor industry
  • 6+ years of experience (or an equivalent amount of education and expereince) in analog and mixed-signal Integrated circuit (IC) design, with DC-DC power converter architectures and control methodologies such as voltage mode control and current mode control
  • Ability to communicate highly technical concepts effectively to both technical and non-technical stakeholders
  • Experience working in Electronic Design Automation (EDA) tools such as EMIR tools capacitive coupling tools and flows, parasitic extraction tools, floating nodes, etc.
  • Experience with production release of power management ICs

Preferred Qualifications: 

  • Masters or PhD in Electrical Engineering
  • Experience with Cadence Virtuoso, Simplis, and ADS
  • Hands-on lab experience supporting high frequency switching power supplies in the semiconductor power management industry

Competitive base salary commensurate with experience: $144,300 - $187,600, relevant for the California Bay Area (subject to change dependent on physical location) 

Posted salary ranges are made in good faith. Qorvo reserves the right to adjust ranges depending on the experience/qualification of the selected candidate as well as external competitiveness and internal comparability. 

Base compensation is one element of Total Rewards offered at Qorvo. More information on the Total Rewards package can be shared upon request. 

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MAKE A DIFFERENCE AT QORVO   

 We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets - we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability. 


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