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Physical Design Cadence Jobs (NOW HIRING)

Futran Tech Solutions Pvt. Ltd.

Physical Design Engineer

$139K - $143K/yr

Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have ... Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys ...

Ambarella

$140K - $156K/yr

Experience with Cadence Innovus/Genus/Conformal and Synopsys Primetime/StarRC would be an added advantage. * Solid understanding of hierarchical physical design strategies, methodologies and ...

Micron

SMTS Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

As the Physical Design Engineer, you will own the complete back-end implementation of a high-speed ... Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and ...

Talent 101, Inc.

Physical Design Engineer

Frisco, TX · On-site

$127K - $131K/yr

What you'll do * Lead end to end Physical Design from floorplan to GDS * Own full PnR flow ... Strong hands on proficiency with Cadence Innovus, Tempus, and Genus * Proven success supporting ...

Micron

SMTS Physical Design Engineer

Folsom, CA · On-site

$145K - $149K/yr

As the Physical Design Engineer, you will own the complete back-end implementation of a high-speed ... Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and ...

Micron

SMTS Physical Design Engineer

Minneapolis, MN · On-site

$142K - $146K/yr

As the Physical Design Engineer, you will own the complete back-end implementation of a high-speed ... Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and ...

DensityAI

Physical Design Engineer

Mountain View, CA · On-site

$230K - $420K/yr

Hands-on with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent ... DFT-aware physical design Compensation Base salary: $230k - $420k USD per year, depending on ...

Mirafra Technology

Physical Design Engineer

San Diego, CA · On-site

$144K - $148K/yr

Cadence Innovas, Synopsys ICC2, PrimetimeSi/Calibre/ etc) Skills: Physical design implementation expertize in latest technology nodes in one of the below domains or all of these. 1. Floor planning at ...

Micron

SMTS Physical Design Engineer

Boise, ID · On-site

$129K - $133K/yr

As the Physical Design Engineer, you will own the complete back-end implementation of a high-speed ... Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and ...

Micron

SMTS Physical Design Engineer

Richardson, TX · On-site

$123K - $127K/yr

As the Physical Design Engineer, you will own the complete back-end implementation of a high-speed ... Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and ...

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Physical Design Cadence information

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$95K

$141.5K

How much do physical design cadence jobs pay per year?

As of Jun 7, 2026, the average yearly pay for physical design cadence in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.
What cities are hiring for Physical Design Cadence jobs? Cities with the most Physical Design Cadence job openings:
Infographic showing various Physical Design Cadence job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 79% Full Time, and 20% Part Time. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.
Chip Lead / Physical Design Director

Chip Lead / Physical Design Director

Cadence Design Systems Inc.

San Jose, CA

$159K - $164K/yr

Full-time

Posted 2 days ago

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are excited to welcome highly talented Physical Design Architects and Chip Leads to join our Cadence Performance Solutions Group (PSG). Working at Cadence means collaborating with some of the industry's brightest minds and driving innovation for the world's most advanced companies. Through Cadence's tools, emulation hardware, and IP products, we have supported a diverse range of customers. Enabling products in data centers, advanced driver-assistance system (ADAS) automotive and physical AI, and cutting-edge artificial intelligence verticals.

As an expert Physical Design Architect, you will engage directly with our leading-edge customers to deliver differentiated RTL-to-GDS services in advanced FinFET nodes. You will lead a talented Physical Design team with the goal of not only meeting but exceeding customers' demanding Performance, Power, Area, and Schedule (PPAS) targets. At Cadence, our customers are at the heart of everything we do, and talented leaders like you are essential to turning this passion into tangible results.

Key Responsibilities
  • Serve as the technical leader for Physical Design and Design for Test teams, driving complex customer SoC projects from RTL or Netlist to GDS. These critical SoCs are targeted for markets such as data centers, automotive, and artificial intelligence.
  • Work directly with customers throughout engagements, from initiation to final GDS delivery, taking ownership of technical decisions, design trade-offs, and innovative problem solving to achieve customer PPA and schedule requirements.
  • Guide customers in selecting the appropriate foundry/node, library, and memory compiler, and establish sign-off criteria to ensure the best features versus cost trade-offs.
  • Collaborate with internal Cadence teams to deliver technical presentations and promote internal AI initiatives to improve quality and efficiency.
  • Work closely with customer or internal RTL/Synthesis teams to ensure that key metrics are achieved efficiently prior to the physical design execution phase gate.
  • Partner with Cadence tools R&D to enhance tools and methodologies to meet and surpass customer requirements.
  • Document and share best practices and lessons learned from ongoing and completed projects to improve efficiency, success rates, and AI adoption in future programs
Job Requirements
  • Fifteen or more years of industry experience in Physical Design.
  • Bachelor's degree in Computer Science/Engineering, Electrical Engineering, or a related field.
  • Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis (including timing constraints).
  • Experience with IC digital implementation flows and backend EDA tools, including Place and Route, Clock Tree Synthesis, IR Drop analysis, backend design timing, and power closure.
  • Demonstrated experience in complete design closure for chip top-level projects.
  • Expertise in PPA optimization, including driving trade-offs between performance, power, and area to meet aggressive design requirements.
  • Experience with advanced nodes at 7nm and below.
  • Proficiency in scripting languages such as Tcl, Perl, or Python is essential.
  • Strong customer-facing communication and problem-solving skills.
  • Personal drive for continuous learning and expanding professional skill sets.
  • Experience in building strong technical relationships with internal stakeholders, including RTL, DFT, CAD, and Library teams.
Preferred Qualifications
  • Master's degree in Computer Science/Engineering, Electrical Engineering, or a related field.
  • Prior experience with IC digital implementation flows and front-end EDA tools, including Synthesis, DFT, and Logical Equivalence Checking.
  • Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus, or with similar tools like ICC, ICC2, DC, or Primetime is highly desired.
  • Experience with advanced nodes at 5nm and below.
  • Domain expertise in CPUs, GPUs, AI Engines, Networks on Chip (NoCs), or high-speed interfaces.
  • Experience with 3D IC design is a significant plus.
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