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Phd In Analog Chip Design Jobs in Connecticut (NOW HIRING)

Quest Global

Physical Design Lead Engineer

Windsor, CT · On-site

$130K - $160K/yr

Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced ... Control timing budgets between blocks & the top-level chip using timing models such as ETM, ILM.

Quest Global

Physical Design Lead Engineer

Windsor, CT · On-site

$130K - $160K/yr

Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced ... Control timing budgets between blocks & the top-level chip using timing models such as ETM, ILM.

Quest Global

Physical Design Lead Engineer

Windsor, CT · On-site

$130K - $160K/yr

Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced ... Control timing budgets between blocks & the top-level chip using timing models such as ETM, ILM.

Skylimit Systems

Electrical Design Engineer

Granby, CT · On-site

$100K - $120K/yr

... analog, digital, or mixed-signal circuit boards and enjoy working in a collaborative engineering ... Design and develop analog, digital, and mixed-signal electronic hardware for aerospace and defense ...

Zachry Group

Engineer III I&C - Nuclear

Stonington, CT · On-site

$98K - $118K/yr

Successful candidate will be relied upon to perform a variety of engineering and design activities ... in analog and digital control systems. Experience Required (minimum) : 6 years (minimum) of ...

Zachry Group

Engineer III I&C - Nuclear

Stonington, CT

$98K - $118K/yr

... in analog and digital control systems. Experience Required (minimum) : 6 years (minimum) of ... Successful candidate will be relied upon to perform a variety of engineering and design activities ...

GAL AeroStaff

FPGA Designer

West Hartland, CT

$122K - $168K/yr

In keeping with this goal, each benefit program has been carefully devised. These benefits include ... Create block diagrams, design concepts, and circuit topologies for FPGA, PLD, digital, and analog ...

Cooper Companies

Senior Electrical Engineer

Trumbull, CT · On-site

$105K - $137K/yr

Expertise in analog and digital circuit design and layout using tools like Altium Schematic Capture. * Strong background in hardware/software integration and hardware debugging using appropriate ...

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Phd In Analog Chip Design information

What is a PhD in analog chip design?

A PhD in Analog Chip Design is a doctoral degree focused on the research, development, and innovation of analog integrated circuits and systems. Students in this program study advanced concepts in analog electronics, including circuit theory, semiconductor device physics, and mixed-signal design. The program typically involves original research that contributes to advancements in areas like low-power design, sensor interfaces, or high-frequency circuits. Graduates are prepared for careers in academia, research institutions, or advanced engineering roles in the semiconductor industry.

What are the key skills and qualifications needed to thrive as a PhD in analog chip design?

To thrive as a PhD in Analog Chip Design, you need deep expertise in analog and mixed-signal circuit design, semiconductor physics, and strong mathematical skills, typically supported by a doctorate in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence, SPICE simulation software, and experience with CMOS process technologies is vital. Strong problem-solving abilities, attention to detail, and effective communication skills help you excel in research, collaboration, and documentation. These skills ensure innovative, reliable chip designs that meet industry standards and drive advancements in electronics.

What are common challenges faced by professionals with a PhD in analog chip design when transitioning from academia to industry roles?

Professionals with a PhD in Analog Chip Design often encounter challenges such as adapting to fast-paced project timelines, aligning research-driven approaches with practical product development needs, and learning to collaborate closely with multidisciplinary teams including digital engineers, layout designers, and product managers. Unlike academic research, industry roles usually require a strong focus on manufacturability, cost constraints, and adherence to strict design specifications. Building effective communication skills and understanding the broader product lifecycle are key to a smooth transition and career growth.

What is the difference between Phd In Analog Chip Design vs Analog IC Design Engineer?

AspectPhd In Analog Chip DesignAnalog IC Design Engineer
Required CredentialsPhD in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering or related field
Work EnvironmentResearch labs, academia, or R&D divisions of companiesDesign teams within semiconductor or electronics companies
Industry UsageAcademic research, advanced R&D, or specialized industry rolesProduct development, circuit design, and manufacturing

The main difference is that a Phd In Analog Chip Design typically involves advanced research, theoretical work, and development of new concepts, often in academic or R&D settings. In contrast, an Analog IC Design Engineer focuses on practical circuit design, implementation, and production within industry settings. Both roles require strong knowledge of analog circuits, but the PhD emphasizes research and innovation, while the engineer role emphasizes application and product development.

What are popular job titles related to Phd In Analog Chip Design jobs in Connecticut?

For Phd In Analog Chip Design jobs in Connecticut, the most frequently searched job titles are:

What job categories do people searching Phd In Analog Chip Design jobs in Connecticut look for?

The top searched job categories for Phd In Analog Chip Design jobs in Connecticut are:

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Cities in Connecticut with the most Phd In Analog Chip Design job openings:

Phd In Analog Chip Design jobs near you

Physical Design Lead Engineer

Quest Global

Windsor, CT • On-site

$130K - $160K/yr

Full-time

Medical, Retirement, PTO

Posted 7 days ago

Quest Global rating

7.8

Company rating: 7.8 out of 10

Based on 11 frontline employees who took The Breakroom Quiz

243rd of 449 rated engineering

Job description

Job Requirements

Company: Quest Global Services-N.A., Inc.

Position Title: Physical Design Lead Engineer

Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and unanticipated client

locations throughout the U.S.

Position Responsibilities: 

Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced process nodes (3nm or below). Take care of floor-planning, CTS (Clock Tree Synthesis), Route use ICC2, Innovus tools related to Cadence and Synopsys. Optimize design with multi-corner multi-mode (MCMM) timing constraint. Fix setup, hold, transition, capacitance, crosstalk violation, min pulse width (MPW), signal EM (Electromigration)

and solving congestion, short, skew, etc. Work on high-speed and complicated clock structure designs with a large number of memories and instances. Use PrimeTime to check and debug timing. Analyze floorplan to reduce congestion using advanced scripting techniques generate a robust clock tree by analyzing the sync points and achieving low latency and minimal power. Work on Static Timing Analysis (STA), Logic Equivalence Checks (LEC), Extraction, Noise, Power. Control timing budgets between blocks & the top-level chip using timing models such as ETM, ILM. Build ECO environments for place and route tools to fix all timing violations. Work on

Power Analysis and IR Drop Analysis to meet the requirements. Work on Physical Verification

(PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS), Antenna, Electrical Rule

Check (ERC), Design for Manufacturing (DFM). Work on logic equivalence check (LEC) for Pre-

Post Place and Route design.

Position Requirements: 

Bachelor’s degree (or foreign equivalent) in Electronics Engineering, or a

related field, PLUS five (5) years of experience in the job offered or a related position. Experience

must include demonstrable knowledge of: The full Place & Route design flow incl. logical

synthesis, STA, DFT, Placement, Clock Tree Synthesis & physical verification; hardening highspeed,

low power CPU designs; design of large SOC full chip & block level P&R using advance

Process technologies: advanced process nodes (3nm or below); high-speed interfaces at chip level;

clock tree creation incl. sync points & achieving low latency & minimal power; design w/ multicorner

multi-mode timing constraints; STA; control of timing budget between blocks & chip using

timing model such as ETM, ILM; ECO environments for place & route tools to fix timing

violations. Travel to unanticipated client locations throughout the U.S., approximately 30%, as

required. May telecommute from any location within the U.S.

Apply at careers.quest-global.com and reference Job Code 28290.0330

Pay Range: $130,333 - $160,000

Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.


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