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Pd Engineer Jobs in California (NOW HIRING)

Broadcom, Inc.

Physical IC Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial ...

Broadcom

Physical IC Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division.This position involves working with the advanced nodes to continue driving next generation Artificial ...

Etched

Physical Design Engineer

Cupertino, CA

$2.0K/mo

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

Etched

Physical Design Engineer

Cupertino, CA · On-site

$2.0K/mo

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

Broadcom Inc.

Physical IC Design Engineer

San Jose, CA · On-site

$150 - $210/hr

Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial ...

Efficient Computer

Physical Design - CAD Lead

San Jose, CA · On-site

$180K - $220K/yr

Work closely with PD team leads to propose and develop end to end build and signoff flows. * Build regression frameworks for ensuring high quality flows and achieve hardware engineering vision of ...

Fictiv

Director of MRO and PD Services

San Francisco, CA · On-site +1

$175K - $190K/yr

Bachelor's degree in Engineering, Business, or related field; MBA preferred * 10+ years of ... MRO and PD service revenue growth and profitability * Customer retention and satisfaction scores

Etched

PD Intern

San Jose, CA · On-site

Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is ... Familiarity with clocking and reset schemes (RTL/PD) * UVM or formal verification experience (DV ...

Apple

Product Design Engineer - Audio Fit

Cupertino, CA · On-site

$159K - $191K/yr

Our Audio Product Design (PD) team creates innovations that enhance music enjoyment, optimize ... You will work with research, design, and engineering teams to create architectures that meet ...

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Showing results 21-40

All JobsPd Engineer JobsPd Engineer Jobs in California

Pd Engineer information

See California salary details

$37.5K

$114.3K

$189K

How much do pd engineer jobs pay per year?

As of Aug 10, 2026, the average yearly pay for pd engineer in California is $114,347.00, according to ZipRecruiter salary data. Most workers in this role earn between $81,900.00 and $149,500.00 per year, depending on experience, location, and employer.

What are some common challenges faced by a Pd engineer when collaborating with cross-functional teams during the product development cycle?

Pd Engineers often work closely with design, manufacturing, and quality assurance teams to bring products from concept to production. One common challenge is ensuring clear communication and alignment on technical requirements, as each team may have different priorities and constraints. Balancing innovation with manufacturability and cost-effectiveness can require creative problem-solving and frequent negotiation. Additionally, Pd Engineers must be adaptable to changes in project scope and timelines, which can arise from evolving customer needs or technical obstacles. Developing strong interpersonal and project management skills is key to overcoming these challenges and delivering successful products.

What are the key skills and qualifications needed to thrive as a Pd engineer, and why are they important?

To thrive as a PD (Physical Design) Engineer, you need a solid background in electronic engineering, digital design principles, and semiconductor physics, usually supported by a relevant bachelor’s or master’s degree. Familiarity with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as experience with scripting languages like TCL or Python, is essential. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set standout PD Engineers apart. These skills are crucial for optimizing chip layouts, ensuring manufacturability, and collaborating efficiently in the fast-paced semiconductor industry.

What is the difference between Pd Engineer vs Process Engineer?

AspectPd EngineerProcess Engineer
Required CredentialsBachelor's degree in Chemical, Mechanical, or related engineering; often requires experience in R&DBachelor's degree in Chemical, Industrial, or Mechanical Engineering; may require process-specific certifications
Work EnvironmentLaboratories, R&D centers, manufacturing facilitiesManufacturing plants, production lines, plant floor
Employer & Industry UsagePharmaceutical, chemical, electronics industriesChemical, manufacturing, oil & gas industries
Common Search & Comparison IntentYesYes

While both Pd Engineers and Process Engineers work within manufacturing and chemical industries, Pd Engineers focus on developing and improving chemical processes, often in R&D settings. Process Engineers typically oversee the day-to-day operation of manufacturing processes, ensuring efficiency and safety. The roles overlap in industry and credentials but differ in focus and work environment.

What is a Pd engineer?

PD Engineers, or Physical Design Engineers, are professionals in the semiconductor industry who are responsible for translating circuit designs into actual hardware layouts on silicon chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and ensuring the chip meets performance, power, and area requirements. PD Engineers use electronic design automation (EDA) tools to optimize the physical implementation of integrated circuits and collaborate closely with design and verification teams to ensure manufacturability and quality. Their work is crucial in the development of modern electronic devices, from smartphones to computers.
What are popular job titles related to Pd Engineer jobs in California? For Pd Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Pd Engineer jobs in California look for? The top searched job categories for Pd Engineer jobs in California are:
What cities in California are hiring for Pd Engineer jobs? Cities in California with the most Pd Engineer job openings:
Pd Engineer jobs near you
Infographic showing various Pd Engineer job openings in California as of August 2026, with employment types broken down into 88% Full Time, 5% Part Time, 2% Temporary, and 5% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $114,347 per year, or $55 per hour.

Physical Design Engineer - Full Chip Implementation

Etched

San Jose, CA • On-site

$2.0K/mo

Full-time

Medical, Dental, Vision

Posted 18 days ago

Job description

About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
Etched is building a new category of AI hardware: frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation-encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs-from synthesis through to GDSII completion. You will lead critical efforts in these areas, leveraging our PD flows to drive aggressive PPA optimization and timing closure. You will collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.
Key Responsibilities
  • Own full-chip clocking across all PVT corners and modes.
  • Manage MMMC (Multi-Mode Multi-Corner) timing closure at the top level.
  • Own timing constraints and hierarchical timing budgeting between top level and blocks.
  • Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
  • Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
  • Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.
  • Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.

You may be a good fit if you have
  • 10+ years of previous experience with chip planning, top level PD, floorplanning
  • Experience with top-level and full-chip closure on advanced process nodes (5nm and below)
  • Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
  • Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
  • Experience with Pegasus or Calibre for physical verification signoff
  • Experience with hierarchical timing budgeting, constraint management, and ECO closure
  • Experience with Cadence Innovus for top-level assembly, routing, and layout fixes
  • Deeply creative and able to think from first principles

Strong candidates may also have experience with
  • Familiarity with modern ML and LLM model architectures
  • Ability to program with Python or another scripting language
  • Familiarity with AI tools for programming/coding
  • Startup experience or comfort working in fast-paced environments

Benefits
  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch and dinner in our office
  • Unlimited compute budget subject to ROI justification

How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

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