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On Target Jobs in Kentucky (NOW HIRING)

QFocus Technologies LLC

$140 - $210/hr

Direct experience bringing up patterns on target silicon and supporting production yield ramp. * ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model ...

Limbs & Things Ltd.

$90 - $130/hr

Remote (based in Los Angeles, California) $Competitive salary + Car Allowance + 30% on-target bonus, with uncapped earning potential REGIONAL ACCOUNT MANAGER We are hiring a Regional Account Manager ...

Uniphore

$290 - $398/hr

Willingness to travel as needed to support the account on-site Compensation Range Below = On Target Earnings - 60/40 Split Hiring Pay Range: $289,600 - $398,200 Benefits In addition to competitive ...

Dermafix Spa

Spa Sales Manager

Lexington, KY

$3.0K/mo

This role offers $100,000+ OTE (On Target Earnings) annually, combining a competitive base salary with uncapped commission potential. This is an exciting opportunity for individuals who excel in ...

Elevate Dental Partners, LLC

$114 - $135/hr

On-target earnings of $55-$65/hour (base pay + production bonus), $5,000 sign-on bonus Benefits and Perks * Monthly bonus program * Paid study clubs + CE allowance * Mentorship & growth opportunities

Dermafix Spa

Sales Manager

Lexington, KY · On-site

$3.0K/mo

Huge earning potential - $100K+ On Target Earnings (OTE) * Employee discounts on spa services and skincare products * Career growth opportunities in a fast-growing company * Work in a high-end ...

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DFT Engineer

QFocus Technologies LLC

On-site

$140 - $210/hr

Other

Posted 4 days ago

Key responsibilities

  • Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG / IEEE standards.

  • Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.

  • Translate pre-silicon ATPG and MBIST patterns into tester formats for ATE deployment and support post-silicon bring-up and debugging.

Job description

As a Senior DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will work closely with front-end design, physical design, verification, and product engineering teams to ensure high test coverage, optimal silicon quality, and streamlined post-silicon manufacturing test enablement.

Key Responsibilities
  • Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).
  • Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.
  • Integrate Memory BIST (MBIST) controllers, repair mechanisms, and custom memory test routines.
  • Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including Stuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.
  • Execute Verilog/SystemVerilog simulations for gate-level DFT validation, ensuring timing and vector cleanliness (SDF simulation).
  • Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT, Tessent, Modus, or TetraMAX)
  • Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) for ATE (Automatic Test Equipment) deployment.
  • Support post-silicon bring-up in the lab, debugging first-silicon DFT features, pattern conversion, and silicon failures.
  • Collaborate with Product and Test Engineering (PTE) teams to optimize test time, diagnose failure modes, and boost manufacturing yield.
Required Qualifications
  • Experience: 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.
  • Core Skills & Technical Expertise:
  • Verilog / SystemVerilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.
  • Scan Insertion: Hands-on experience with scan synthesis, compressed scan architectures (EDT/SmartTest), and boundary scan integration.
  • ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
  • MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
  • JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
  • Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.
  • ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
  • MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
  • JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
  • Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.
Preferred Skills
  • Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.
  • Knowledge of advanced DFT concepts like High-Speed IO testing, SerDes loopback, or Analog DFT.
  • Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes.

QFocus Technologies LLC is an Equal Employment Opportunity employer.

We are a group of passionate and experienced technology professionals working together with a singular focus to delight our customers by delivering quantifiable value and becoming a natural extension of your team!

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