Neural Network Jobs (NOW HIRING)

Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. 

As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations. 

We are seeking a Principal Neural Network Microarchitect to lead the definition of Rivian’s next-generation Neural Network Engine (NNE) microarchitecture. This role is aligned to Rivian’s Professional track at RIV-8 (Principal), where the expectation is broad technical expertise, ownership of critical design matters, and work that shapes future products and technologies.

You will drive the architecture of the NNE core with emphasis on datapath design, scheduling, quantization-aware execution, partitioning, and performance scalability for production neural network workloads. At Rivian, the RAP1 SoC NNE includes a large processing array, configurable partitioning, instruction DMA engines, data DMA engines, and substantial on-chip SRAM, making this a deeply cross-functional architecture role spanning compute, memory movement, software interfaces, and system constraints.

• Define and evolve the NNE core microarchitecture, including compute datapaths, instruction flow, scheduling strategy, quantization support, and execution efficiency for neural network inference workloads.
• Architect solutions that map effectively onto Rivian’s NNE hardware model, including the processing array, partitioning strategy, and coordination of instruction and data movement across the engine.
• Drive architectural tradeoffs across performance, power, area, utilization, latency, and scalability.
• Lead definition of mechanisms for efficient movement of activations, weights, and outputs through on-chip and off-chip memory pathways and DMA architecture.
• Partner closely with compiler, model, firmware, verification, and SoC teams to ensure neural network workloads are translated into efficient executable flows for the NNE. Rivian’s compiler flow translates network descriptions into instruction streams executed on the NNE, so tight hardware-software co-design is essential.
• Define architectural requirements for correctness, observability, resiliency, and debuggability, including support for error handling, recovery hooks, and safe execution flows where needed.
• Build performance models, evaluate bottlenecks, and guide decisions with data across representative production workloads.
• Influence long-range NNE direction, establish technical principles, and serve as a key architecture voice across the silicon organization. At the RIV-8 level, this role is expected to contribute to company objectives and use broad expertise to resolve critical issues and broad design matters.
• Mentor engineers across architecture and implementation disciplines and raise the technical bar for neural network accelerator design at Rivian.

• Deep expertise in computer architecture and hardware microarchitecture, with a strong track record designing complex silicon blocks from concept through production.
• Strong understanding of neural network inference hardware, including datapath design, scheduling, numerical formats, quantization, and performance optimization.
• Experience architecting or optimizing specialized compute engines such as NPUs, AI accelerators, vector/tensor processors, or systolic-array-based architectures.
• Strong knowledge of memory hierarchy and data movement, including SRAM organization, DMA-based transfer models, buffering, bandwidth management, and latency hiding.
• Experience working across hardware and software boundaries, especially with compiler, runtime, or model deployment teams.
• Proven ability to evaluate architectural tradeoffs using modeling, analysis, and empirical workload characterization.
• Excellent communication skills and the ability to influence across architecture, design, verification, physical design, firmware, compiler, and product teams.
• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.

• Experience with automotive or safety-aware silicon development.
• Experience with neural network workloads such as CNNs, transformers, RNNs, or related model classes used in perception and autonomy contexts.
• Familiarity with instruction-driven accelerator architectures, partitioned compute fabrics, and high-efficiency memory orchestration.
• Experience defining architecture for systems that must balance throughput, determinism, power efficiency, and debuggability.

The listed base salary range for this role is $218,000 - $312,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.

We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com. 

Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law.

Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at candidateaccommodations@rivian.com.

Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes (“Candidate Personal Data”). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. 

Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services. 

Rivian may transfer or store internationally your Candidate Personal Data, including to or in the United States, Canada, the United Kingdom, and the European Union and in the cloud, and this data may be subject to the laws and accessible to the courts, law enforcement and national security authorities of such jurisdictions.  

Please note that we are currently not accepting applications from third party application services.

• Deep expertise in computer architecture and hardware microarchitecture, with a strong track record designing complex silicon blocks from concept through production.
• Strong understanding of neural network inference hardware, including datapath design, scheduling, numerical formats, quantization, and performance optimization.
• Experience architecting or optimizing specialized compute engines such as NPUs, AI accelerators, vector/tensor processors, or systolic-array-based architectures.
• Strong knowledge of memory hierarchy and data movement, including SRAM organization, DMA-based transfer models, buffering, bandwidth management, and latency hiding.
• Experience working across hardware and software boundaries, especially with compiler, runtime, or model deployment teams.
• Proven ability to evaluate architectural tradeoffs using modeling, analysis, and empirical workload characterization.
• Excellent communication skills and the ability to influence across architecture, design, verification, physical design, firmware, compiler, and product teams.
• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.

• Experience with automotive or safety-aware silicon development.
• Experience with neural network workloads such as CNNs, transformers, RNNs, or related model classes used in perception and autonomy contexts.
• Familiarity with instruction-driven accelerator architectures, partitioned compute fabrics, and high-efficiency memory orchestration.
• Experience defining architecture for systems that must balance throughput, determinism, power efficiency, and debuggability.