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Modem Asic Design Engineer Jobs (NOW HIRING)

SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers ...

SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers ...

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers ...

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers ...

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers ...

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Modem Asic Design Engineer information

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$49.5K

$118.6K

$173.5K

How much do modem asic design engineer jobs pay per year?

As of Jun 7, 2026, the average yearly pay for modem asic design engineer in the United States is $118,589.00, according to ZipRecruiter salary data. Most workers in this role earn between $100,000.00 and $137,000.00 per year, depending on experience, location, and employer.

What is the difference between Modem Asic Design Engineer vs Wireless Communication ASIC Engineer?

AspectModem Asic Design EngineerWireless Communication ASIC Engineer
Primary FocusDesigning ASICs for modems, including signal processing and data transmissionDesigning ASICs for wireless communication systems, including RF and baseband components
Required SkillsDigital design, FPGA/ASIC development, signal processingRF design, digital ASIC development, wireless protocols
Work EnvironmentSemiconductor companies, telecom equipment manufacturersWireless device manufacturers, telecom industry

Both roles involve ASIC design and require digital design skills, but Modem Asic Design Engineers focus on modem-specific components, while Wireless Communication ASIC Engineers specialize in wireless system ASICs. The choice depends on your interest in either data transmission or wireless protocols.

What does a Modem ASIC Design Engineer do?

A Modem ASIC Design Engineer is responsible for designing and developing Application-Specific Integrated Circuits (ASICs) used in modem hardware. They work on creating efficient, high-performance chips that enable wireless communication in devices such as smartphones, tablets, and IoT devices. Their role involves collaborating with system architects, writing hardware description language (HDL) code, verifying designs, and optimizing for power, area, and performance. These engineers play a crucial part in ensuring that modems can handle complex communication protocols and deliver reliable connectivity.

What are the key skills and qualifications needed to thrive as a Modem ASIC Design Engineer, and why are they important?

To thrive as a Modem ASIC Design Engineer, you need a solid background in digital design, signal processing, and hardware description languages (such as Verilog or VHDL), typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools (like Synopsys or Cadence), simulation environments, and experience in RTL coding and verification are essential. Strong problem-solving skills, attention to detail, and effective teamwork make someone stand out in this position. These skills and qualities are crucial for designing high-performance, reliable modem chips that meet stringent industry standards and project deadlines.

What are the most common challenges faced by Modem ASIC Design Engineers during the verification phase, and how are they typically addressed?

Modem ASIC Design Engineers often encounter challenges such as ensuring thorough coverage of complex protocol standards and debugging issues that arise during simulation and hardware testing. These challenges are typically addressed by using advanced verification methodologies like UVM, collaborating closely with verification and firmware teams, and employing automated test benches to simulate real-world scenarios. Regular code reviews and design walkthroughs also help identify potential problems early, leading to more robust and reliable modem ASICs.
Infographic showing various Modem Asic Design Engineer job openings in the United States as of May 2026, with employment types broken down into 1% Internship, 95% Full Time, 1% Temporary, and 3% Contract. Highlights an 86% Physical, 9% Hybrid, and 5% Remote job distribution, with an average salary of $118,589 per year, or $57 per hour.
Principal ASIC Design Engineer (Starshield)

Principal ASIC Design Engineer (Starshield)

SpaceX

Hawthorne, CA

$200K - $285K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 4 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

12th of 59 rated aerospace companies


Job description

PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD)

Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

  • Design digital ASICs and/or FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
  • Work closely with verification team to ensure all aspects of the design are covered and verified.
  • Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
  • Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 8+ years of experience in RTL implementation and/or FPGA/ASIC development.

PREFERRED SKILLS AND EXPERIENCE:

  • Experience solving problems including clock domain crossings and power optimization.
  • Experience developing complex ASICs.
  • Experience with multicore CPU subsystem design.
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.).
  • Experience with embedded processors.
  • Experience with high speed and low power design techniques.
  • Scripting skills (Python, TCL etc.).
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
  • Enjoy being challenged and learning new skills.

ADDITIONAL REQUIREMENTS:

  • Ability to work long hours and weekends as necessary to support critical milestones.
  • Willingness to travel for off-site testing.
  • An active TS-SCI clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.

COMPENSATION AND BENEFITS:    

Pay range:    
Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $20,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.


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