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Mid Level Sram Circuit Design Jobs (NOW HIRING)

Geologics

Circuit Design Engineer

Orlando, FL · Hybrid

$71/hr

Role: Circuit Design Engineer Client: Defense-Aerospace Hourly Rate: up to $71/hr (W2, non ... Collaborate with mechanical and packaging engineers to resolve board level constraints. * Liaise ...

Geologics

Circuit Design Engineer

Orlando, FL · Hybrid

$71/hr

Role: Circuit Design Engineer Client: Defense-Aerospace Hourly Rate: up to $71/hr (W2, non ... Collaborate with mechanical and packaging engineers to resolve board level constraints. * Liaise ...

Connect Tech+Talent

Mid-Level Hardware Engineer

Austin, TX

$122K - $161K/yr

Mid-Level Hardware Engineer Austin, TX Contract We are seeking a skilled and hands-on Mid-Level ... The ideal candidate brings a strong foundation in analog circuit design, enjoys solving real-world ...

Connect Tech+Talent

Mid-Level Hardware Engineer

Austin, TX · On-site

$122K - $161K/yr

Mid-Level Hardware Engineer Austin, TX Contract We are seeking a skilled and hands-on Mid-Level ... The ideal candidate brings a strong foundation in analog circuit design, enjoys solving real-world ...

Lockheed Martin Corporation

As a Circuit Design Engineer, you will work on the development of a sophisticated state-of-the-art ... level testing.

Qualcomm

CPU SRAM Design Engineer

Austin, TX · On-site

As a CPU SRAM Design Engineer, you will design, improve, and analyze digital circuits for memories ... Experience with circuit simulation and monte carlo analysis. * Experience with static timing ...

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Mid Level Sram Circuit Design information

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How much do mid level sram circuit design jobs pay per year?

As of Jul 29, 2026, the average yearly pay for mid level sram circuit design in the United States is $101,072.00, according to ZipRecruiter salary data. Most workers in this role earn between $82,500.00 and $115,500.00 per year, depending on experience, location, and employer.
What cities are hiring for Mid Level Sram Circuit Design jobs? Cities with the most Mid Level Sram Circuit Design job openings:
What are the most commonly searched types of Sram Circuit Design jobs? The most popular types of Sram Circuit Design jobs are:
What states have the most Mid Level Sram Circuit Design jobs? States with the most job openings for Mid Level Sram Circuit Design jobs include:
Mid Level Sram Circuit Design jobs near you
Infographic showing various Mid Level Sram Circuit Design job openings in the United States as of July 2026, with employment types broken down into 94% Full Time, 5% Part Time, and 1% Contract. Highlights an 93% Physical, 1% Hybrid, and 6% Remote job distribution, with an average salary of $101,072 per year, or $48.6 per hour.

SRAM Layout Design Engineer (Only W2)

Trispark Inc

Santa Clara, CA • On-site

Other

Posted 15 days ago

Job description

Sr. SRAM Layout Design Engineer

Salary- 120k

Below are his pointers to streamline our screening:

Tsmc 3nm or lower

SRAM 

Mixed signal Analog not needed

Min 10years experience 

What you will be doing:

· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.

· Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.

· Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.

· Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.

· Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.

· Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.

· Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.

· Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.

· Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

What we need to see:

· Have a BSEE or equivalent experience

· 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.

· Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.

· Solid grasp of SRAM and memory layout principles.

· Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.

· Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.

· Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.

· Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.

· Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.

· Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.

· Knowledge of layout automation or AI tools is a definite plus.

Apply