Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... Translate architecture into microarchitecture & RTL implementation * Design and integrate Ethernet ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... Translate architecture into microarchitecture & RTL implementation * Design and integrate Ethernet ...
RISC-V CPU Microarchitecture / RTL
Santa Clara, CA · On-site +1
$100K - $500K/yr
RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position ... Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor ...
RISC-V CPU Microarchitecture / RTL
Santa Clara, CA · On-site +1
$100K - $500K/yr
RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position ... Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor ...
We are seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture to help define, design, and deliver next‑generation GPU IP. The ideal candidate ...
We are seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture to help define, design, and deliver next‑generation GPU IP. The ideal candidate ...
You will drive the microarchitecture and RTL implementation of scalable on-chip communication ... This is a senior, hands‑on engineering role with broad technical ownership. You will drive design ...
You will drive the microarchitecture and RTL implementation of scalable on-chip communication ... This is a senior, hands‑on engineering role with broad technical ownership. You will drive design ...
RTL Design Engineer - Interconnect & Network Datapath
San Francisco, CA · On-site
$225K - $445K/yr
You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting ... This is a senior engineering role with broad technical ownership and substantial direct RTL work.
RTL Design Engineer - Interconnect & Network Datapath
San Francisco, CA · On-site
$225K - $445K/yr
You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting ... This is a senior engineering role with broad technical ownership and substantial direct RTL work.
Description As a RTL Engineer, you will participate in the following: • Microarchitecture ... development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will participate in the following: • Microarchitecture ... development and specification - from early high-level architectural exploration through micro ...
RISC-V CPU Microarchitecture / RTL
Santa Clara, CA · On-site
$100K - $500K/yr
RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position ... Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor ...
RISC-V CPU Microarchitecture / RTL
Santa Clara, CA · On-site
$100K - $500K/yr
RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position ... Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor ...
You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting ... This is a senior engineering role with broad technical ownership and substantial direct RTL work.
You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting ... This is a senior engineering role with broad technical ownership and substantial direct RTL work.
Description As a RTL Engineer, you will participate in the following: • Microarchitecture ... development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will participate in the following: • Microarchitecture ... development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will participate in the following: • Microarchitecture ... development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will participate in the following: • Microarchitecture ... development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will participate in the following: • Microarchitecture ... development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will participate in the following: • Microarchitecture ... development and specification - from early high-level architectural exploration through micro ...
RTL Engineer
Mountain View, CA · On-site
$160K/yr
What You'll Do: * Own RTL design of digital blocks/subsystems for our accelerator ... Drive microarchitecture trade-offs - pipelining, datapath vs. control, clock/power gating - for ...
RTL Engineer
Mountain View, CA · On-site
$160K/yr
What You'll Do: * Own RTL design of digital blocks/subsystems for our accelerator ... Drive microarchitecture trade-offs - pipelining, datapath vs. control, clock/power gating - for ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Lead RTL Engineer
Austin, TX · On-site
$101K - $133K/yr
Lead RTL Engineer Location: Austin, TX (Onsite) Key Skills * RTL Lead experience * Processor/CPU ... Microarchitecture and Architecture Ownership Responsibilities * Translate architecture ...
Lead RTL Engineer
Austin, TX · On-site
$101K - $133K/yr
Lead RTL Engineer Location: Austin, TX (Onsite) Key Skills * RTL Lead experience * Processor/CPU ... Microarchitecture and Architecture Ownership Responsibilities * Translate architecture ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
RTL Engineer
Mountain View, CA · On-site
$215K - $300K/yr
What You'll Do: * Own RTL design of digital blocks/subsystems for our accelerator ... Drive microarchitecture trade-offs - pipelining, datapath vs. control, clock/power gating - for ...
RTL Engineer
Mountain View, CA · On-site
$215K - $300K/yr
What You'll Do: * Own RTL design of digital blocks/subsystems for our accelerator ... Drive microarchitecture trade-offs - pipelining, datapath vs. control, clock/power gating - for ...
RTL Engineer
Austin, TX · On-site
$215K - $300K/yr
What You'll Do: * Own RTL design of digital blocks/subsystems for our accelerator ... Drive microarchitecture trade-offs -- pipelining, datapath vs. control, clock/power gating -- for ...
Quick apply
RTL Engineer
Austin, TX · On-site
$215K - $300K/yr
What You'll Do: * Own RTL design of digital blocks/subsystems for our accelerator ... Drive microarchitecture trade-offs -- pipelining, datapath vs. control, clock/power gating -- for ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Description As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro ...
Microarchitecture Rtl Engineer information
See salary details
$82.5K - $90.2K
4% of jobs
$90.2K - $98K
4% of jobs
$98K - $105.7K
0% of jobs
$105.7K - $113.4K
0% of jobs
$113.4K - $121.1K
0% of jobs
$121.1K - $128.9K
0% of jobs
$128.9K - $136.6K
4% of jobs
$136.6K - $144.3K
2% of jobs
$144.3K - $152K
0% of jobs
$152K - $159.8K
0% of jobs
$160.7K is the 25th percentile. Wages below this are outliers.
$159.8K - $167.5K
85% of jobs
$82.5K
$158.2K
$167.5K
How much do microarchitecture rtl engineer jobs pay per year?
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Staff RTL Engineer Ethernet Saratoga, CA Full-Time
Saratoga, CA • On-site
Other
Re-posted 13 days ago
Job description
Saratoga, CA
Full-Time
Join a cutting-edge hardware company building next-generation networking silicon to accelerate AI training and inference.
We’re seeking a Staff RTL Engineer to help architect and implement high-performance Ethernet subsystems (MAC, PCS, SerDes) for advanced Networking ICs.
Key Responsibilities-
Translate architecture into microarchitecture & RTL implementation
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Design and integrate Ethernet IO subsystems (MAC/PCS/PHY/SerDes)
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Perform RTL coding, debug, and design reviews
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Collaborate with Verification, Physical Design & Firmware teams
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Support post-silicon bring-up and productization
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MSEE with 8–15 years of ASIC/RTL design experience
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Strong expertise in Ethernet 802.3 protocols (Layer 2/3/4)
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Experience integrating MAC + PCS + SerDes (100G+ preferred)
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Solid understanding of SerDes fundamentals (DFE, CTLE, clocking)
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Multiple successful networking ASIC tape-outs
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Strong knowledge of ASIC design flow, DFT & physical implementation
If you're passionate about high-speed networking and AI infrastructure silicon, apply today.