ZipRecruiter

Log In

1

Memory Design Engineer Jobs in San Ramon, CA (NOW HIRING)

Western Digital

EDA- CAD Engineer

San Jose, CA

Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A * Programming Skills: Strong proficiency in scripting languages such as Python, Tcl, Perl, or ...

Micron

Senior Semiconductor Design Engineer

San Jose, CA · On-site

$163K - $246K/yr

Design and develop non-volatile 3D-NAND memory array drivers and sensing circuits. Plan wordline ... Mentor and train junior engineers in simulation, modeling, and design methodologies. Employer will ...

Western Digital

EDA- CAD Engineer

San Jose, CA · On-site

Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A * Programming Skills: Strong proficiency in scripting languages such as Python, Tcl, Perl, or ...

Western Digital

EDA- CAD Engineer

San Jose, CA · On-site

$145K - $194K/yr

Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A * Programming Skills: Strong proficiency in scripting languages such as Python, Tcl, Perl, or ...

Micron

Staff Design Integration Lead

San Jose, CA

$145K - $246K/yr

... Engineering NAND Flash build team at Micron is dedicated to developing world-class memory solutions ... As the Staff Design Integration Lead, you will take on a pivotal role in full chip level ...

Hark

Manufacturing Design Engineer

San Jose, CA

$150K - $300K/yr

... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We are looking for an incredible Manufacturing Design Engineer to bridge the gap ...

Hark

Manufacturing Design Engineer

San Jose, CA · On-site

$150K - $300K/yr

... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We are looking for an incredible Manufacturing Design Engineer to bridge the gap ...

Taara Connect, Inc

Board Design Engineer

Sunnyvale, CA · On-site

Taara is seeking a Board Design Engineer to lead the complete printed circuit board design from ... Designing the analog and digital circuitry including high speed transceivers, power, memory, and ...

Apple

Hardware Design Engineer

Sunnyvale, CA · On-site

As a Mixed Signal Hardware Design Engineer, you will be responsible for the design, implementation ... memory systems Experience with circuit schematic capture/layout Experience interacting with ...

Broadcom

IC Design Engineer

San Jose, CA

Understanding of programming issues such as OO design, memory leaks, data structures, sorting, recursion, stack overflow and greedy algorithms. * Strong problem-solving skills, attention to detail ...

Baidu USA

Senior RTL Design Engineer

Sunnyvale, CA · On-site

... memory subsystems. Knowledge of RISC-V architecture is a plus. Proficiency with hardware (RTL ... quality design. Ability to work well with others and a belief that engineering is a team sport.

Baidu USA

Senior RTL Design Engineer

Sunnyvale, CA · On-site

... and memory subsystems. • Knowledge of RISC-V architecture is a plus. • Proficiency with ... design. • Ability to work well with others and a belief that engineering is a team sport. • ...

next page

Showing results 1-20

All JobsMemory Design Engineer JobsMemory Design Engineer Jobs in San Ramon, CA

Memory Design Engineer information

See San Ramon, CA salary details

$90K

$158K

$324.6K

How much do memory design engineer jobs pay per year?

As of Jun 27, 2026, the average yearly pay for memory design engineer in San Ramon, CA is $157,963.00, according to ZipRecruiter salary data. Most workers in this role earn between $106,200.00 and $176,600.00 per year, depending on experience, location, and employer.

What are the primary challenges faced by Memory Design Engineers on a daily basis?

Memory Design Engineers often encounter challenges such as optimizing memory circuits for speed, power efficiency, and area while ensuring manufacturability and meeting reliability standards. Balancing these conflicting requirements requires strong analytical skills and close collaboration with verification, process, and layout teams. The role also involves troubleshooting design issues, staying updated with evolving semiconductor technologies, and ensuring timely project delivery. Overcoming these challenges fosters professional development and helps engineers build a solid track record in advanced technology nodes.

What are the key skills and qualifications needed to thrive in the Memory Design Engineer position, and why are they important?

A Memory Design Engineer requires a strong background in electrical engineering, semiconductor physics, and digital/analog circuit design, typically supported by a relevant bachelor's or master's degree. Expertise with EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages and memory characterization tools is essential. Strong problem-solving skills, attention to detail, and effective communication are important soft skills in this role. These competencies are crucial to ensure reliable, high-performance memory designs that meet rigorous industry standards and enable smooth collaboration within multidisciplinary engineering teams.

What engineers make $500,000?

Senior Memory Design Engineers in the semiconductor industry or related fields can earn $500,000 or more annually, especially with extensive experience, advanced skills in VLSI design, and working at major tech or chip manufacturing companies. High compensation often includes bonuses, stock options, and other incentives for top-tier engineers in specialized roles.

What does a memory design engineer do?

A memory design engineer develops and optimizes integrated circuit memory components, such as RAM and cache, ensuring they meet performance, power, and reliability specifications. They use electronic design automation tools and work closely with chip architects and verification teams throughout the design process.

What is the salary of memory layout design engineer?

The salary of a memory layout design engineer typically ranges from $80,000 to $130,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in VLSI design and EDA tools may earn higher compensation, often supplemented with bonuses and benefits.

What is a Memory Design Engineer job?

A Memory Design Engineer is responsible for designing, developing, and optimizing memory circuits such as SRAM, DRAM, or flash memory. They work on transistor-level design, layout, simulation, and verification to ensure performance, power efficiency, and reliability. Engineers collaborate with process, verification, and product teams to meet design specifications and manufacturing constraints. Their role is critical in advancing memory technology for applications in consumer electronics, computing, and enterprise solutions.

What jobs can DT get you?

A Memory Design Engineer can pursue roles such as integrated circuit designer, hardware engineer, or system architect in semiconductor companies. These positions involve designing and optimizing memory components, often requiring knowledge of digital design, verification tools, and industry standards.
What job categories do people searching Memory Design Engineer jobs in San Ramon, CA look for? The top searched job categories for Memory Design Engineer jobs in San Ramon, CA are:
Memory Design Engineer jobs near you
Staff Engineer, IP Design (ASIC)

Staff Engineer, IP Design (ASIC)

SK hynix memory solutions America Inc.

San Jose, CA

Full-time

Medical, Dental, Vision, Life, Retirement

Posted 14 days ago

Job description

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.


About the Team

You will join the System on Chip (SoC) Design Team at SK Hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions. As a Staff Engineer, you will own critical High speed interface IP, drive methodology improvements (such as AI-assisted design flows), and mentor engineers to ensure first-pass silicon success.

Responsibilities

  • Design and verification of the high speed interface for next generation storage subsystem for NVME or Chiplet.
  • Drive team efforts with multi-function teams from RTL development through silicon bring-up.

Minimum Qualifications

  • 8 years of experience in ASIC design and deep knowledge in the design and integration of PCle logic.
  • Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
  • Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
  • Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

Preferred Qualifications

  • Experience in PCle(Gen4/5/6) architecture in TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
  • Proven experience with Link training, power state(L0/L0P/L1/L2), error handling (AER).
  • Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
  • Good plus to have experience in AI Assist design flow.

Education

  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.