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Memory Design Engineer Jobs in San Ramon, CA (NOW HIRING)

Physical design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Senior Principal Physical Design Engineer (Top-Level Floorplanning & STA) Location: San Jose ... Responsibilities · Own the full-chip top-level floorplan: die/partition planning, macro and memory ...

... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...

Staff Design Engineer

San Jose, CA · On-site

$145K - $246K/yr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...

Staff Design Engineer

San Jose, CA · On-site

$145K - $246K/yr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...

Staff Design Engineer

San Jose, CA · On-site

$145K - $246K/yr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...

Staff Design Engineer

San Jose, CA · On-site

$145K - $246K/yr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...

Principal Design Engineer

San Jose, CA · On-site

$176K - $298K/yr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... The Principal Design Engineer in Micron's NVEG organization contributes to the development of new ...

Senior RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL ...

Principal Design Engineer

San Jose, CA · On-site

$176K - $298K/yr

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... The Principal Design Engineer in Micron's NVEG organization contributes to the development of new ...

Senior RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL ...

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL ...

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Design Engineer in Micron's Pathfinding Design Team, you will play a key role in shaping next ...

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Design Engineer in Micron's Pathfinding Design Team, you will play a key role in shaping next ...

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Memory Design Engineer information

See San Ramon, CA salary details

$90K

$158K

$324.6K

How much do memory design engineer jobs pay per year?

As of Jun 26, 2026, the average yearly pay for memory design engineer in San Ramon, CA is $157,963.00, according to ZipRecruiter salary data. Most workers in this role earn between $106,200.00 and $176,600.00 per year, depending on experience, location, and employer.

What are the primary challenges faced by Memory Design Engineers on a daily basis?

Memory Design Engineers often encounter challenges such as optimizing memory circuits for speed, power efficiency, and area while ensuring manufacturability and meeting reliability standards. Balancing these conflicting requirements requires strong analytical skills and close collaboration with verification, process, and layout teams. The role also involves troubleshooting design issues, staying updated with evolving semiconductor technologies, and ensuring timely project delivery. Overcoming these challenges fosters professional development and helps engineers build a solid track record in advanced technology nodes.

What are the key skills and qualifications needed to thrive in the Memory Design Engineer position, and why are they important?

A Memory Design Engineer requires a strong background in electrical engineering, semiconductor physics, and digital/analog circuit design, typically supported by a relevant bachelor's or master's degree. Expertise with EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages and memory characterization tools is essential. Strong problem-solving skills, attention to detail, and effective communication are important soft skills in this role. These competencies are crucial to ensure reliable, high-performance memory designs that meet rigorous industry standards and enable smooth collaboration within multidisciplinary engineering teams.

What engineers make $500,000?

Senior Memory Design Engineers in the semiconductor industry or related fields can earn $500,000 or more annually, especially with extensive experience, advanced skills in VLSI design, and working at major tech or chip manufacturing companies. High compensation often includes bonuses, stock options, and other incentives for top-tier engineers in specialized roles.

What does a memory design engineer do?

A memory design engineer develops and optimizes integrated circuit memory components, such as RAM and cache, ensuring they meet performance, power, and reliability specifications. They use electronic design automation tools and work closely with chip architects and verification teams throughout the design process.

What is the salary of memory layout design engineer?

The salary of a memory layout design engineer typically ranges from $80,000 to $130,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in VLSI design and EDA tools may earn higher compensation, often supplemented with bonuses and benefits.

What is a Memory Design Engineer job?

A Memory Design Engineer is responsible for designing, developing, and optimizing memory circuits such as SRAM, DRAM, or flash memory. They work on transistor-level design, layout, simulation, and verification to ensure performance, power efficiency, and reliability. Engineers collaborate with process, verification, and product teams to meet design specifications and manufacturing constraints. Their role is critical in advancing memory technology for applications in consumer electronics, computing, and enterprise solutions.

What jobs can DT get you?

A Memory Design Engineer can pursue roles such as integrated circuit designer, hardware engineer, or system architect in semiconductor companies. These positions involve designing and optimizing memory components, often requiring knowledge of digital design, verification tools, and industry standards.
What job categories do people searching Memory Design Engineer jobs in San Ramon, CA look for? The top searched job categories for Memory Design Engineer jobs in San Ramon, CA are:

Physical design Engineer

Skywaves MP LLC

San Jose, CA • On-site

$159K - $164K/yr

Other

Posted 8 days ago


Job description

Job Title: Senior Principal Physical Design Engineer (Top-Level Floorplanning & STA)
Location: San Jose / Austin
Job Type:  Onsite
Experience : Relevant minimum 7+ years required and senior also fine.
Responsibilities
·       Own the full-chip top-level floorplan: die/partition planning, macro and memory placement, and pin/port alignment across block boundaries
·       Define partition abutment, repeating structures, and channel/feedthrough strategy to enable clean block integration
·       Drive top-level PPA optimization (power, performance, area) across the chip hierarchy
·       Plan and review the top-level power grid / PDN in coordination with EM/IR sign-off
·       Author and maintain top-level SDC and timing budgets; partition constraints down to block owners
·       Collaborate with ASIC vendor, IP partners, and block-level PD engineers on floorplan, partition, and STA reviews
 
Tools
·       Cadence Innovus
·       Synopsys Fusion