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Memory Controller Rtl Design Engineer Jobs (NOW HIRING)

Architect Labs

Design and implement memory controllers : including DDR5/LPDDR5X PHY-side controller logic, HBM3 ... Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related ...

Mythic

Senior RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Develop and optimize high-performance, low-power components such as datapaths, controllers, memory ...

Mythic

Senior RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Develop and optimize high-performance, low-power components such as datapaths, controllers, memory ...

Mythic

RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in ... including datapaths, controllers, memory subsystems, and interconnects. * Collaborate with ...

Mythic

Senior RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Develop and optimize high-performance, low-power components such as datapaths, controllers, memory ...

Mythic

Senior RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Develop and optimize high-performance, low-power components such as datapaths, controllers, memory ...

Mythic

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in ... including datapaths, controllers, memory subsystems, and interconnects. * Collaborate with ...

Mythic

RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in ... including datapaths, controllers, memory subsystems, and interconnects. * Collaborate with ...

Lumilens

IC/RTL Design Engineer

San Jose, CA · On-site

IC/RTL Design Engineer/ Front-End Engineer About the role. You design and implement the digital ... Exposure to scale-up / scale-out interconnects or network switch / NIC / memory-controller ...

Mythic

Senior RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Develop and optimize high-performance, low-power components such as datapaths, controllers, memory ...

Mythic

Senior RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Develop and optimize high-performance, low-power components such as datapaths, controllers, memory ...

Mythic

RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in ... including datapaths, controllers, memory subsystems, and interconnects. * Collaborate with ...

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Memory Controller Rtl Design Engineer information

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How much do memory controller rtl design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for memory controller rtl design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are popular job titles related to Memory Controller Rtl Design Engineer jobs?

For Memory Controller Rtl Design Engineer jobs, the most frequently searched job titles are:

Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)

San Jose, CA • On-site

AIT Global, Inc.
IT Services • 51 - 200 employees
Learn more about AIT Global, Inc.external

Other

This job post has expired today. Applications are no longer accepted.

Job description

Job Title: Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)
Location: San Jose, CA
Role Summary:
We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub Interface Gateway) protocol and DDR/LPDDR/HBM PHY-facing DFI (DFI Interface). This role owns modifying and extending an existing memory controller design to accommodate new architectural requirements, protocol updates, and performance targets.

Key Responsibilities:
  • Modify and extend an existing memory controller RTL design to support new CHI-G protocol requirements
  • and DFI interface changes
  • Own microarchitecture updates for command scheduling, arbitration, QoS, and bank/rank management
  • within the memory controller
  • Design and integrate CHI-G request/response/snoop channel logic, ensuring protocol compliance and
  • coherency correctness
  • Develop and maintain DFI-compliant interface logic (command, write/read data, timing parameters) to PHY
  • Analyze impact of new features on timing, power, and area; drive RTL changes through synthesis and STA
  • closure
  • Collaborate with verification, DFT, and physical design teams to ensure the modified design meets
  • functional and PPA (Power, Performance, Area) goals
  • Debug pre-silicon and post-silicon issues related to memory controller behavior, coherency, and interface
  • timing
  • Produce/update microarchitecture specs, interface timing diagrams, and design documentation reflecting the
  • new changes
  • Participate in design reviews and mentor junior engineers on CHI-G/DFI concepts
Required Qualifications:
  • Bachelor's/Master's in Electrical Engineering, Computer Engineering, or related field
  • 8+ years of RTL design experience in SystemVerilog/Verilog for SoC subsystems
  • Hands-on experience with memory controller design (DDR4/DDR5/LPDDR) or equivalent
  • Working knowledge of ARM CHI/CHI-G protocol (coherency, request/response/snoop channels)
  • Working knowledge of APB/AHB/AXI4/ACE interfaces
  • Experience with the DFI specification and PHY-facing timing/command interfaces
  • Experience modifying/extending existing large RTL codebases (not greenfield-only experience)
  • Familiarity with synthesis, timing closure, and low-power design techniques
  • Strong debugging skills using simulation waveforms, formal tools, and lab equipment
Preferred Qualifications:
  • Exposure to DFT, post-silicon bring-up, or PCB-level memory subsystem validation
  • Familiarity with UVM-based verification flows (to collaborate effectively with verification teams)
  • Experience with AI/LLM-assisted RTL development or design productivity tooling

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