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Medical Product Verification Engineer Jobs (NOW HIRING)

Design Verification Engineer

San Diego, CA

$144K - $176K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock ...

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock ...

We are now looking for a GPU Verification Engineer. NVIDIA is seeking best-in-class ASIC ... product lines ranging from consumer graphics to self-driving cars and the growing field of ...

Design Verification Engineer

Broomfield, CO · On-site

$137K - $167K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock ...

Design Verification Engineer

Broomfield, CO

$137K - $167K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock ...

Formal Verification Engineer

Austin, TX · On-site

$134K/yr

You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make ... Description As a formal verification engineer working the complete formal verification for single ...

Design Verification Engineer

Irvine, CA

$146K - $178K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock ...

Lead SoC Verification Engineer

Los Altos, CA · On-site

$161K/yr

As our Lead SoC Verification Engineer, you will help establish the verification and validation methodology for our end product. Responsibilities * Cross Functional reviews: Participate in ...

Wireless Radio Verification Engineer

Irvine, CA · On-site

$146K/yr

You'll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Wireless Radio Verification Engineer, you'll ensure first-time ...

Lead SoC Verification Engineer

Los Altos, CA · On-site

$161K/yr

As our Lead SoC Verification Engineer, you will help establish the verification and validation methodology for our end product. Responsibilities * Cross Functional reviews: Participate in ...

Showing results 41-60

Medical Product Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do medical product verification engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for medical product verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a medical product verification engineer do?

A Medical Product Verification Engineer is responsible for testing and evaluating medical devices to ensure they meet regulatory standards, safety requirements, and design specifications. They develop and execute test plans, analyze data, and document results to verify that products perform as intended. This role often involves collaborating with design, quality, and regulatory teams to address any issues found during verification. Their work is critical in ensuring that medical products are safe and effective before reaching the market.

What are the key skills and qualifications needed to thrive as a medical product verification engineer, and why are they important?

To thrive as a Medical Product Verification Engineer, you need a strong background in biomedical engineering or a related field, with expertise in product testing, quality assurance, and regulatory standards. Familiarity with tools such as verification protocols, test automation software, and compliance with FDA or ISO 13485 regulations is essential. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills for this role. These skills and qualities ensure medical products are safe, effective, and meet rigorous regulatory requirements, directly impacting patient outcomes and company reputation.

What are some common challenges faced by medical product verification engineers during product testing, and how can they be addressed?

Medical Product Verification Engineers often encounter challenges such as ensuring test protocols comply with strict regulatory standards and managing tight project timelines. Variability in device performance and unexpected test failures can also occur, requiring quick problem-solving and collaboration with design and quality teams. Addressing these challenges involves maintaining clear documentation, participating in cross-functional meetings, and staying updated on regulatory changes to ensure testing processes remain compliant and efficient.

What is the difference between Medical Product Verification Engineer vs Medical Device Quality Assurance Specialist?

AspectMedical Product Verification EngineerMedical Device Quality Assurance Specialist
CredentialsBachelor's in Engineering, certifications in verification/validationBachelor's in Life Sciences or Engineering, certifications in QA
Work EnvironmentDesign labs, testing facilities, R&D departmentsManufacturing sites, quality control labs, compliance offices
Employer & Industry UsageMedical device companies, biotech firmsMedical device manufacturers, healthcare companies
Common Search & ComparisonYesYes

Medical Product Verification Engineers focus on testing and validating medical devices to ensure they meet specifications, working closely with R&D teams. Medical Device Quality Assurance Specialists concentrate on maintaining quality standards, compliance, and regulatory requirements throughout manufacturing. Both roles are essential in the medical device industry but differ in their primary focus and responsibilities.

What are popular job titles related to Medical Product Verification Engineer jobs?

For Medical Product Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Medical Product Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 80% Full Time, and 20% Contract. Highlights an 100% In-person job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Design Verification Engineer

San Diego, CA

Broadcom
Semiconductor and Electronic Component Manufacturing • 10K+ employees

$144K - $176K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 24 days ago


Key responsibilities

  • Define verification plans and environment architecture for complex digital and mixed-signal IP blocks.

  • Develop test cases, test bench components, and perform coverage analysis and closure.

  • Analyze and debug simulation failures at RTL and gate-level, working closely with design teams and EDA vendors.


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz


Job description

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Job Description:

Design Verification Engineer

Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom's ASIC developments.

The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate the block, system, and ASIC level verification. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks.

The candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.

Requirements:

  • 12+ years of experience with verification concepts and architectures for complex digital and MXS circuits

  • Experience verifying designs at the block and system levels.

  • Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)

  • Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits

  • Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)

  • Experience with Synopsys, Cadence, and Mentor simulations tools

  • Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments

  • Experience with Perl/Python and Tcl or other scripting languages

  • Experience with version control systems (DesignSync, git)

  • Superior writing, grammar, and verbal communication skills

  • Excellent problem solver; develops and employs automated processes where applicable

  • Worked independently and in a global team and dynamic environment in a highly visible role

  • Possesses ability to learn and adapt to new tools and methodologies on the fly

  • Must have legal authorization to work in the US

It is a plus if the candidate has expertise in one or more of the following areas:

  • Experience with hardware design and debug

  • Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms

  • Formal verification concepts / experience is a plus

  • Experience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus

  • Experience with co-simulation a plus

Education and Experience required:

  • BS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.


Compensation and Benefits


The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.


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