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Manager Rf Antenna Design Engineer Jobs in Toronto, ON

Amd

RTL Design Engineer

Thornhill, ON · Hybrid

An RTL Design Engineering role in our Security IP (SECIP) team, where a large number of individual ... Your expertise will impact security policy management, cryptography, data compression, high ...

J.S. Held LLC

Design Engineer

Toronto, ON · Hybrid

CA$121K - CA$135K/yr

The Design Engineer (P. Eng.) brings strong design experience and carries the main responsibility ... Experience managing a team is an asset. * Extensive experience with Parts 3,4 & 9 of the Ontario ...

Radian Robotics

Mechanical Design Engineer

Hamilton, ON · On-site

CA$80K - CA$100K/yr

Job Summary Mechanical Design Engineer Radian Robotics Full-time In-Office | Hamilton, ON, Canada The Opportunity Reporting to the Mechanical Engineering Manager, the Mechanical Design Engineer will ...

Relay

Senior Design Engineer

Toronto, ON · On-site

$130.50 - $159.50/hr

Partner closely with product managers, designers, and engineers to ensure shipped experiences meet a high standard for quality, usability, and polish. * Own and evolve Telegraph, our design system.

Actalent

Mechanical Design Engineer

Toronto, ON · On-site

CA$50 - CA$70/hr

Job Title: Mechanical Design Engineer Location: OTTAWA Join an innovative technology team ... management, and manufacturability considerations * Proven experience bringing products into high ...

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Manager, Physical Design Engineer

Astera Labs

Toronto, ON • On-site

Full-time

Re-posted 29 days ago

Key responsibilities

  • Lead the physical design implementation of connectivity ASICs from RTL to GDSII, including floorplanning, place-and-route, and sign-off.

  • Collaborate with cross-functional teams such as RTL, DFT, STA, EMIR, and verification to ensure design convergence and quality.

  • Build, mentor, and manage a team of physical design engineers, overseeing team development, hiring, and project execution.

Job description

Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
  • 10+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
  • 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
  • Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
  • Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
  • Strong scripting ability in Tcl, Python, and/or Perl.
  • Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
  • Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

  • Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
  • Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
  • Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
  • Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
  • Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
  • Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
  • Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
  • Experience with Cadence and/or Synopsys physical design tools/flows.

Preferred Experience/Nice to Have

  • Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
  • Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
  • Track record of building and scaling physical design teams through multiple tapeouts.
  • Knowledge of agentic AI solutions for EDA automation.

Base salary range is CAD 180,000 to CAD 220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

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