Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams ... Work closely with device engineers to tune process conditions. Optimize critical dimensions (CD ...
Lithography Process Engineer information
See Portland, OR salary details
$52.5K - $61.5K
2% of jobs
$61.5K - $70.4K
9% of jobs
$78.6K is the 25th percentile. Wages below this are outliers.
$70.4K - $79.4K
15% of jobs
$79.4K - $88.4K
18% of jobs
The median wage is $91.4K / yr.
$88.4K - $97.3K
17% of jobs
$97.3K - $106.3K
14% of jobs
$106.5K is the 75th percentile. Wages above this are outliers.
$106.3K - $115.3K
11% of jobs
$115.3K - $124.2K
6% of jobs
$124.2K - $133.2K
4% of jobs
$133.2K - $142.2K
3% of jobs
$142.2K - $151.1K
1% of jobs
$52.5K
$97.6K
$151.1K
How much do lithography process engineer jobs pay per year?
What are the key skills and qualifications needed to thrive as a Lithography Process Engineer, and why are they important?
What does a Lithography Process Engineer do?
What is the difference between Lithography Process Engineer vs Semiconductor Process Engineer?
| Aspect | Lithography Process Engineer | Semiconductor Process Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering, Materials Science, or related fields; certifications in process engineering | Bachelor's or Master's in Chemical, Electrical, or Materials Engineering; similar certifications |
| Work Environment | Cleanroom environments focused on photolithography steps in chip fabrication | Cleanroom or fab environments covering multiple process steps in semiconductor manufacturing |
| Industry Usage | Primarily in semiconductor fabrication plants, focusing on lithography processes | Across semiconductor manufacturing, including process development and production |
While both roles operate in semiconductor manufacturing and require similar technical backgrounds, the Lithography Process Engineer specializes in photolithography techniques, whereas the Semiconductor Process Engineer oversees broader process steps. The Lithography Process Engineer focuses on patterning and imaging, making their role more specialized within the manufacturing process.
What are some common challenges faced by Lithography Process Engineers and how can they be addressed?
Full-time, Part-time
Medical, Life, Retirement, PTO
This job post has expired today. Applications are no longer accepted.
Intel rating
8.8
Based on 143 frontline employees who took The Breakroom Quiz
8th of 139 rated electronics manufacturers
Job description
Join Intel and build a better tomorrow.
What we do: The Intel Foundry MDCE and Logic Technology development (LTD) organizations delivers process technology innovation to drive Intel's product roadmap.
What we offer:
We give you opportunities to transform technology and create a better future by delivering products that touch the lives of every person on earth.
As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.
We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).
We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative perks that make Intel a Great Place to Work.
We give you opportunities to transform technology and create a better future by delivering products that touch the lives of every person on earth.
Benefits:
We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative rewards that make Intel a Great Place to Work Find more information about our amazing benefits here.
The ideal candidate should exhibit behavioral traits that indicate:
Job Responsibilities include but are not limited to:
1. Process Flow Development
Develop and define integrated front end process flows for new technology nodes.
Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams.
Establish process windows and integration schemes.
2. Yield and Defect Reduction
Analyze yield loss and parametric failures.
Perform root cause analysis using statistical tools (SPC, DOE, FMEA).
Drive corrective actions to improve yield and cycle time.
3. Device Performance Optimization
Ensure electrical parameters meet design targets.
Work closely with device engineers to tune process conditions.
Optimize critical dimensions (CD), overlay, and film thickness.
4. Process Control and Monitoring
Implement control plans and process monitoring strategies.
Use statistical tools such as: Cpk / Ppk, Control charts, Capability analysis
5. Technology Transfer
Support ramp from RnD to high-volume manufacturing (HVM).
Document process specifications and standard operating procedures (SOPs).
6. Cross-Functional Collaboration/Work with
Device Engineering
Equipment Engineering/Module Engineering
Yield Engineering
Reliability Teams
Design Teams
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a PhD degree in one of these fields: Electrical Engineering, Physics, Applied Physics, Optics, Material Science, Chemical Engineering, Mechanical Engineering, or related discipline.
Candidate must possess at least one of the following:
6+ months experience on one or more of the following areas:
o Semiconductor device fabrication or nanotechnology.
o Electrical characterization of transistors or other semiconductor devices.
o Clean room process development.
Preferred Qualifications:
JMP, MATLAB, Scripting languages (1.e. Python, JSL, TCL), or programming languages (1.e. SQL, C/C++).
Strong understanding of Device physics (CMOS, FinFET, GAA, etc)
Hand on experience in VLSI device fabrication and testing in the lab.
Knowledge of basic VLSI fabrication instruments (1.e. mechanism of dry etcher, ALD (atomic layer deposition), PE CVD, metallization, etc.)
Understanding statistical process control and charting methodology data flow and integrity. Strong data analysis and presentation acumen.
Integrated process knowledge, including strong design of experiments and model-based problem-solving skills for complex problems, excursions, and defects.
Knowledge of automation and defect classification systems in a fab environment.
Strong stakeholder management and influencing skills. Experience in coordination with other departments, co-workers, etc.
Interview Tips here.
By applying to this posting your resume and profile will become visible to Intel Recruiters and will allow them to consider you for current and future job openings aligned with the skills and positions mentioned above.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
Other Locations
US, Phoenix
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in the US $116,100.00-$163,800.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will require an on-site presence.* Job posting details (such as work model, location or time type) are subject to change.
- Other
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968