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Lec Engineer Jobs (NOW HIRING)

Redolent, Inc.

US_West | Network Design Engineer_L3

$102K - $140K/yr

Synopsys/Cadence EDA Tools (Priority: 1) LEC (Priority: 2) STA/Constraints (Priority: 2) Named Job ... Digital Design (RTL) Engineer * Local Skills : Julie Skidmore * Languages Required: : English

Apple

Graphics FE Integration Engineer

Austin, TX

$147K - $272K/yr

Experience with scalable designs, DFT insertion, LEC, Lint and codeline management. Ability to ... Proficiency in programming techniques. Experience with RTL analysis and/or PPA optimization using ...

Apple

Graphics FE Integration Engineer

Austin, TX

$147K - $272K/yr

Experience with scalable designs, DFT insertion, LEC, Lint and codeline management. Ability to ... Proficiency in programming techniques. Experience with RTL analysis and/or PPA optimization using ...

Ethan Alexander Group

dft engineer - 1293079

Irvine, CA · On-site

... LEC), and timing closure * Support test engineer for pattern generation, tester debug and failure ... analysis. * Work with Test Engineering team during Silicon bring-up and creating flow/scripts ...

Glow Networks

RTL Design Engineer

Dallas, TX · On-site

RTL Design Engineer Location: Santa Clara, CA/Remote Minimum 10 years of strong experience in ... synthesis, LEC and STA. Debugging and fixing functional break. • Take ownership of tasks and ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...

Apple

Graphics FE Integration Engineer

Austin, TX

$181K - $318K/yr

Description As a GPU Design Integration Engineer, you will be responsible for: - RTL integration ... Experience with RTL analysis and/or PPA optimization using Invio, LEC and Genus. Familiarity with ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...

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All JobsLec Engineer Jobs

Lec Engineer information

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$39K

$101.8K

$137.5K

How much do lec engineer jobs pay per year?

As of Jun 5, 2026, the average yearly pay for lec engineer in the United States is $101,752.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,000.00 and $116,500.00 per year, depending on experience, location, and employer.

What are LEC Engineers?

LEC Engineers, or Lift and Escalator Consultants/Engineers, are professionals who specialize in the design, installation, maintenance, and safety compliance of lifts (elevators) and escalators in buildings. They ensure that these systems meet legal and safety standards, work efficiently, and are suitable for the specific needs of a building or infrastructure project. LEC Engineers often work closely with architects, builders, and facility managers to provide technical expertise throughout the lifecycle of vertical transportation systems.

What is the difference between Lec Engineer vs Electrical Engineer?

AspectLec EngineerElectrical Engineer
CredentialsDiploma or Bachelor's in Electrical or Electronics EngineeringBachelor's or higher in Electrical Engineering or related fields
Work EnvironmentEducational institutions, training centers, or technical institutesIndustrial plants, power stations, construction sites, or corporate offices
Primary ResponsibilitiesTeaching, training, and curriculum development for electrical systemsDesign, development, and maintenance of electrical systems and equipment
Industry UsageEducational and training sectorsPower, manufacturing, construction, and consulting industries

While Lec Engineers focus on teaching and training in electrical topics within educational settings, Electrical Engineers are involved in designing and maintaining electrical systems in various industries. Both roles require a background in electrical engineering, but their work environments and primary duties differ significantly.

What are the key skills and qualifications needed to thrive as a LEC Engineer, and why are they important?

To thrive as a LEC (Lighting, Electrical, and Controls) Engineer, you need a strong background in electrical engineering principles, lighting design, and control systems, typically supported by a relevant engineering degree and professional licensure. Familiarity with CAD software, lighting calculation tools (such as DIALux or AGi32), and knowledge of industry codes and standards are essential. Excellent problem-solving, communication, and project management skills help differentiate top performers in this field. These competencies are crucial for designing safe, efficient, and compliant electrical and lighting systems that meet client and regulatory requirements.

What are the typical collaboration dynamics between a LEC Engineer and other engineering teams during a project?

LEC Engineers (Low-Voltage Electrical Control Engineers) frequently collaborate with mechanical, civil, and other electrical engineering teams throughout a project's lifecycle. They coordinate closely during the design phase to integrate control systems with building infrastructure, and during implementation to ensure compatibility with other systems. Effective communication and regular meetings are common to address technical challenges, align on project milestones, and ensure safety standards are met. This collaborative environment not only fosters learning but also helps LEC Engineers broaden their skill sets and advance professionally.
Infographic showing various Lec Engineer job openings in the United States as of May 2026, with employment types broken down into 50% Full Time, and 50% Contract. Highlights an 100% In-person job distribution, with an average salary of $101,752 per year, or $48.9 per hour.

ASIC Design-for-Test (DFT) Engineer

Vkore Solutions

San Jose, CA • On-site

Contractor

Posted 2 days ago

Job description

Job Title – ASIC Design-for-Test (DFT) Engineer

Location: San Jose, CA (Onsite)

Job Type: Contract

 

Job Description

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

 

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

 

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • 10+ years of hands-on experience in ASIC Design-for-Test (DFT)
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

 

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.