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Lead Ic Verification Engineer Jobs (NOW HIRING)

Anodize

Lead SoC Verification Engineer

Los Altos, CA · On-site

$161K/yr

Lead SoC Verification Engineer Summary We're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced ...

Anodize

Lead SoC Verification Engineer

Los Altos, CA · On-site

$161K/yr

Lead SoC Verification Engineer Summary We're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced ...

Cirrus Logic

Design Verification Engineer

Chandler, AZ · On-site

$133K - $163K/yr

... signal IC solutions. You will be responsible for end-to-end functional verification across block ... Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.

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How much do lead ic verification engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for lead ic verification engineer in the United States is $123,784.00, according to ZipRecruiter salary data. Most workers in this role earn between $102,500.00 and $135,000.00 per year, depending on experience, location, and employer.

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Infographic showing various Lead Ic Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 9% Part Time, and 2% Contract. Highlights an 89% Physical, 3% Hybrid, and 8% Remote job distribution, with an average salary of $123,784 per year, or $59.5 per hour.

Principal Engineer, Digital Verification Engineering

Chandler, AZ • On-site

Analog Devices
Electrical Equipment, Appliance, and Component Manufacturing • 5 - 10K employees
Learn more about Analog Devicesexternal

Full-time

Re-posted 25 days ago

Analog Devices rating

8.7

Company rating: 8.7 out of 10

Based on 19 frontline employees who took The Breakroom Quiz

Job description

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
As a Principal Design Verification Engineer, you will own verification strategy and closure for complex analog and mixed-signal ICs, from verification planning through tape-out sign-off. You will drive the adoption of AI/ML techniques to improve regression efficiency, debug throughput, and coverage closure. Your work will span multiple business units, ensuring product quality and accelerating delivery across ADI's next-generation mixed-signal and power management products.
Key Responsibilities
  • Drive adoption of AI/ML methodologies for failure clustering, regression triage, anomaly detection, and intelligent coverage optimization
  • Define and own verification strategy, plans, and success metrics across block, top-level, and system contexts for mixed-signal ICs
  • Build and scale mixed-signal verification infrastructure including reusable SystemVerilog/UVM testbenches, monitors, scoreboards, and automated checkers
  • Lead functional coverage planning, closure analysis, and sign-off for tape-out readiness
  • Drive silicon correlation by comparing simulation expectations against lab measurements, refining models and tests based on measured behavior
  • Lead verification architecture and methodology reviews, influencing best practices across projects
  • Collaborate with design, applications, and test teams to ensure verification reflects real use-cases, operating modes, and corner scenarios
Required Skills and Experience
  • MSEE or MSCE with 10+ years of IC verification experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered)
  • Expert-level proficiency in SystemVerilog and UVM with a track record of building coverage-driven verification environments for mixed-signal products
  • Track record of owning end-to-end verification readiness from planning through tape-out sign-off and production release
  • Strong Python scripting skills with experience applying AI/ML techniques to enhance verification productivity
  • Deep knowledge of formal verification, assertion-based methodology, and clock domain crossing analysis
  • Proficiency with Cadence verification tools: Xcelium (simulation), JasperGold (formal verification)
  • Excellent presentation, technical writing, and communication skills
Preferred Qualifications
  • Experience with mixed-signal and AMS verification techniques including Verilog-AMS, real-number modeling, and behavioral abstraction
  • Experience with gate-level simulation, SDF back-annotation, and post-layout verification
  • Background verifying power management and interface-rich mixed-signal devices across multiple power domains
  • Strong analytical and problem-solving abilities
  • Ability to work effectively in a collaborative team environment
Technical Scope
  • Development and deployment of AI/ML-driven workflows for regression analytics, failure classification, and debug acceleration
  • Full verification ownership from specification analysis through coverage closure and tape-out sign-off
  • Mixed-signal verification environment architecture including analog behavioral modeling and digital-analog interface checking
  • Verification methodology definition including test plan authoring, coverage model design, and regression management
Collaboration and Impact
  • Champion AI/ML-driven improvements to verification workflows, sharing results and best practices across teams
  • Partner with design, applications, and test teams to translate product requirements into verification coverage that reflects real operating conditions
  • Contribute to organizational knowledge through verification reviews, methodology forums, and cross-team technical exchanges

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days

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About Analog Devices

Sourced by ZipRecruiter

Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.

Industry

Electrical equipment, appliance, and component manufacturing

Company size

5,001 - 10,000 Employees

Headquarters location

Norwood, MA, US

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