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Junior Rtl Design Engineer Jobs in Pasadena, CA (NOW HIRING)

Astrolab

Principal FPGA Engineer

Hawthorne, CA · Hybrid

$203K - $243K/yr

The Principal FPGA Engineer will participate in all aspects of the development and test of avionics ... The ideal candidate has 15+ years of experience in FPGA firmware development including RTL design ...

Astrolab

Staff FPGA Engineer

Hawthorne, CA · On-site

$170K - $226K/yr

We work collaboratively across engineering disciplines to deliver reliable, high-performance ... The ideal candidate has 10+ years of experience in FPGA development including RTL design ...

Astrolab

Staff FPGA Engineer

Hawthorne, CA · On-site

$170K - $226K/yr

Staff FPGA Engineer Department: Avionics Employment Type: Full Time Location: Hawthorne, California ... The ideal candidate has 10+ years of experience in FPGA development including RTL design ...

Actalent

Design Engineer Powertrain

Sun Valley, CA

$100K - $130K/yr

Design Engineer - Powertrain We are seeking a talented Design Engineer specializing in Powertrain ... Review and approve 3D models and 2D drawings and specifications created by junior engineers.

SprintRay

Senior Design Engineer

Los Angeles, CA · On-site

$155K - $175K/yr

Mentor junior engineers and contribute to design reviews, best practices, and continuous improvement. * Support production issues, failure analysis, and post-launch design improvements. Required ...

Apple

Wireless SOC FW Engineer

Los Angeles, CA · On-site

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...

jobr.pro

Senior Mechanical Design Engineer

Los Angeles, CA · On-site

$150 - $180/hr

Mentor junior engineers and contribute to design reviews and best practices. What Success Looks Like * Mechanical systems delivered on time from requirements through commissioning with minimal rework.

New

Apple

Wireless SOC FW Engineer

Los Angeles, CA · On-site

... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...

Senior plc

Design Engineer - CATIA

Burbank, CA

... engineering lab, allowing us to design, manufacture, and qualify complex ducting systems for space ... However, experienced employees are expected to help mentor junior employees as needed.

Senior plc

Design Engineer - CATIA

Burbank, CA · On-site

... engineering lab, allowing us to design, manufacture, and qualify complex ducting systems for space ... However, experienced employees are expected to help mentor junior employees as needed.

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All JobsRtl Design Engineer JobsJunior Rtl Design Engineer JobsJunior Rtl Design Engineer Jobs in Pasadena, CA

Junior Rtl Design Engineer information

See Pasadena, CA salary details

$36.5K

$78.3K

$119.4K

How much do junior rtl design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for junior rtl design engineer in Pasadena, CA is $78,319.00, according to ZipRecruiter salary data. Most workers in this role earn between $52,900.00 and $87,300.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

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Junior Rtl Design Engineer jobs near you

Principal FPGA Engineer

Astrolab

Hawthorne, CA • Hybrid

$203K - $243K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 20 days ago

Job description

Description
Venturi Astrolab, Inc. (Astrolab) is pioneering new ways to explore and operate on distant planetary bodies. We are singularly focused on designing, building, and operating a fleet of multi-purpose commercial planetary rovers to extend and enhance humanity’s presence in the solar system. We are seeking motivated, creative, and exceptional people to join our world-class team.    
The Avionics team is responsible for all aspects of the electrical systems and hardware on Astrolab’s electric rover vehicles and ground support equipment.  We work collaborative with all teams at Astrolab to provide exceptionally capable and reliable electronics to serve our missions.   
The Principal FPGA Engineer will participate in all aspects of the development and test of avionics FPGA RTL designs for Astrolab rovers. The ideal candidate has 15+ years of experience in FPGA firmware development including RTL design, simulations, analysis, verification, and HW testing. 
This position will report to the Director of Avionics Engineering and will be based in our Hawthorne, CA office. 


What you'll do:
  • Own FPGA RTL development from blank sheet to flight
  • Develop FPGA logical architecture and requirements in collaboration with other engineering disciplines including defining HW/SW interfaces between fabric logic and processing subsystems
  • Develop RTL code for Microsemi, Xilinx, or other FPGA or SoC devices in either SystemVerilog or VHDL
  • Perform design verification including simulations, test benches, timing analysis, and hardware testing
  • Lead design reviews, demonstrate requirement traceability, and create documentation for FPGA operation and interfacing with other SW and FPGA systems
  • Develop and participate in test campaigns ranging from unit level manual tests, unit automated tests, and system level tests

What You'll Bring
  • Bachelor of Science degree in Computer Engineering, Electrical Engineering, or equivalent
  • 15+ years of experience in FPGA RTL architecture, development, verification, deployment, and maintenance
  • Skilled at SystemVerilog or VHDL
  • Skilled in at least 1 scripting language (TCL, shell, Python, etc) 
  • Skilled in verification techniques, and timing/stability analysis
  • Proficiency in understanding PCB designs and reading schematics
  • Proficiency in understanding embedded software
  • Proficiency with AXI protocols (at least AXI4 family)
  • Knowledge of common bus and memory interfaces (DDR4, SPI, I2C, UART, etc)
  • Demonstrated success working in a dynamic environment
Additional Responsibilities 
  • Design for space environments including radiation impacts and mitigations

What We Offer:
  • Join a team of best-in-class engineers building the foundation of planetary surface exploration
  • Equity ownership in the company
  • Comprehensive health benefits, including medical, dental, vision, and mental health support
  • 401(k) plan with company match
  • Flexible PTO and parental leave
  • Home office set up reimbursement
  • Fully flexible and remote friendly work environment
  • Weekly lunch stipend, plus complimentary snacks and beverages on-site
  • Once a month social hour on-site with food and drinks